A 48–56 GHz >1 dBm-HB1dB Sub-Sampling Eight-Path-Filter Receiver With Fully-Integrated LO Generation and On-Chip Antenna

Abstract

This article presents a 48–56 GHz mixer-first fourth-harmonic sub-sampling eight-path-filter receiver integrating an on-chip differential dipole antenna, a six-port hybrid coupler, and an eight-phase 12.5-duty-cycle local oscillator (LO) generator with phase and duty-cycle calibration. A sub-sampling gapped eight-path-filter configuration is proposed to relax LO operating frequency and rise/fall time requirements so that LO power consumption can be reduced significantly. An on-chip antenna (OCA) employs crossed artificial-magnetic-conductor patterns to improve its power gain. A six-port transformer-based quadrature hybrid coupler is employed for both input matching and radio frequency (RF) quadrature signal generation. Fabricated in Taiwan Semiconductor Manufacturing Company (TSMC) 28 nm CMOS technology, the receiver prototype achieves a peak gain of 17.3 dB, a minimum noise figure (NF) of 14.7 dB, IP1dB of −12 dBm, a peak in-band IIP3 of +4.0 dBm, an out-of-band (OOB)-B1dB of +0.8 dBm, and >1 dBm HB1dB while consuming 80.2–99.7 mW. With the OCA, the receiver system achieves a peak gain of 11 dB, demonstrating a maximum 3.6 Gb/s data rate at an air distance of 25 cm.