A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Injection-Locked Clock Multiplier Utilizing a Complementary-Injection Scheme and an Adaptive Pulsewidth Adjustment

Abstract

This article presents a ring voltage-controlled oscillator (RVCO)-based pulse-injection-locked clock multiplier (ILCM) with a complementary-injection scheme, an adaptive pulsewidth adjustment, and a hybrid frequency tracking loop (FTL). The developed complementary-injection scheme introduces a combination of traditional narrow-pulse injection and wide-pulse injection to achieve phase error cancellation and enhance noise suppression. Based on the derived optimal pulsewidth principle, the proposed adaptive pulsewidth adjustment technique automatically maintains the optimal noise suppression across process, voltage, and temperature (PVT) variations. To achieve enhanced in-band noise suppression and extend the locking range, a hybrid FTL that incorporates a conventional phase-locked loop (PLL), a developed timing-adjusted loop (TAL), and an automatic locking mechanism (ALM) is designed. Fabricated in a 28-nm CMOS process, the ILCM occupies an active area of 0.133 mm2. The measurement results show that it achieves 43.9-fs rms jitter and −59.1-dBc spur level. The calculated figure-of-merit (FoM) is −255.5 dB, which outperforms other state-of-the-art works.