{"title":"A Time-Domain Current-Mode Buck Converter With a PI Compensator Incorporating an Infinite Phase Shift Delay Line","authors":"Mao-Ling Chiu;I-Fang Lo;Tsung-Hsien Lin","doi":"10.1109/JSSC.2024.3486083","DOIUrl":null,"url":null,"abstract":"This article presents a current-mode buck converter that incorporates two control paths implemented using time-domain (TD) signal processing. The voltage regulation path (VRP) ensures high-accuracy output voltage, while the current feed-forward path (CFFP) simplifies the compensator design. A TD proportional-integral (PI) compensator is proposed, which consists of an infinite phase shift delay line (IPSDL) and a voltage-controlled oscillator (VCO) in cascade. The IPSDL enables the converter to support a wide frequency range with improved transient performance. The converter is fabricated using a 180-nm CMOS process and can provide <inline-formula> <tex-math>$V_{\\text {OUT}}$ </tex-math></inline-formula> ranging from 0.4 to 2.3 V from a 3.3-V input, supporting both continuous-conduction mode and discontinuous-conduction mode (DCM) operations. The load regulation (LR) is 5.26 mV/A. The load-transient settling time is <inline-formula> <tex-math>$8.4~{\\mu }$ </tex-math></inline-formula>s when the output current steps from 1 A to 50 mA and <inline-formula> <tex-math>$3~{\\mu }$ </tex-math></inline-formula>s when transitioning from 50 mA to 1 A. At <inline-formula> <tex-math>$V_{\\text {OUT}}$ </tex-math></inline-formula> of 1.8 V, the measured peak efficiency is 95.7%.","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"60 6","pages":"2206-2214"},"PeriodicalIF":5.6000,"publicationDate":"2024-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Journal of Solid-state Circuits","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10742657/","RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q1","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
This article presents a current-mode buck converter that incorporates two control paths implemented using time-domain (TD) signal processing. The voltage regulation path (VRP) ensures high-accuracy output voltage, while the current feed-forward path (CFFP) simplifies the compensator design. A TD proportional-integral (PI) compensator is proposed, which consists of an infinite phase shift delay line (IPSDL) and a voltage-controlled oscillator (VCO) in cascade. The IPSDL enables the converter to support a wide frequency range with improved transient performance. The converter is fabricated using a 180-nm CMOS process and can provide $V_{\text {OUT}}$ ranging from 0.4 to 2.3 V from a 3.3-V input, supporting both continuous-conduction mode and discontinuous-conduction mode (DCM) operations. The load regulation (LR) is 5.26 mV/A. The load-transient settling time is $8.4~{\mu }$ s when the output current steps from 1 A to 50 mA and $3~{\mu }$ s when transitioning from 50 mA to 1 A. At $V_{\text {OUT}}$ of 1.8 V, the measured peak efficiency is 95.7%.
期刊介绍:
The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuits modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.