A 93.6-dB SNDR Fully Dynamic CT-DT Noise-Shaping SAR ADC With Closed-Loop Capacitively Coupled Two-Stage FIA

Abstract

This article presents an embedded-friendly high-precision two-step noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) designed for sensor applications. By employing a continuous-time (CT) SAR to track the input signal, the design avoids the kT/C noise typically induced by sampling operations. This approach decouples the signal-to-noise ratio (SNR) from the size of the sampling capacitor, thus relaxing the burden of the input and reference buffers. The CT SAR is followed by a two-stage floating-inverter-amplifier (FIA)-based closed-loop residue amplifier (RA) with a 94.6-dB open-loop gain, effectively mitigating interstage gain error. Furthermore, the CT-DT NS SAR exhibits high energy efficiency and fully dynamic characteristics due to the proposed RA and the second-stage DT NS SAR. Fabricated in a 55-nm CMOS process, the prototype achieves a signal-to-noise and distortion ratio (SNDR) of 93.6 dB with only a 120-fF single-ended input capacitor at a signal bandwidth of 5 kHz. Operating at a 1-MHz operating rate, the prototype consumes $34.7~{\mu }$ W from a 1.2-V supply, resulting in a Schreier figure of merit (FoM) of 175.2 dB.