A 1920 × 1080 Array 2-D/3-D Image Sensor With 3-μ s Row-Time Single-Slope ADC and 100-MHz Demodulated PPD Locked-In Pixel

Abstract

This article presents a $1920{\times } 1080$ array 2-D/3-D image sensor with 3- $\mu $ s row-time single-slope ADC (SSADC) and 100-MHz demodulated locked-in pixel. To obtain reliable depth information, a backside-illuminated $6{\times } 6~{\mu }$ m pinned photodiode (PPD) pixel with high built-in electric field is used to accelerate charge transfer. Storage diodes (SDs) are designed to collect demodulated electrons for correlated double sampling (CDS) readout. The two-tap pixel and differential multiplexing readout architecture realize both image modes (2-D and 3-D) working with full-HD resolution. To overcome the limitation of quantization speed in conventional structures, we introduce a 4-bit time-to-digital converter (TDC) into the 8-bit SSADC for residual information quantization, achieving 3- $\mu $ s row-time and 12-bit readout accuracy. In addition, we have proposed a detection and correction circuit in the data stitching process, which resolves error code problem. The common-mode output of two different taps is removed through full differential readout for the background light (BGL) canceling. A prototype chip is fabricated in a 110-nm backside illumination CMOS image sensor (BSI CIS) process. The designed PPD enabled a low depth noise of under 0.43% over the range of 0.3–1.5 m, with a modulation frequency of 100 MHz. By adopting the high-speed SSADC, the 2-D and 3-D frame rates achieve 300 and 60 frames/s, respectively.