Dual-Input Stacked Inverter-Based Single-Ended DRAM Sense Amplifier Using BL Switches for Low-Power High-Speed Sensing

Abstract

Dynamic random access memory (DRAM) sensing capabilities have deteriorated with the reduced supply voltage and cell capacitance as the DRAM process scales down. Previous bitline sense amplifiers (BLSAs) use offset-canceling (OC) techniques based on capacitive coupling or current mirrors. However, these OC techniques induce substantial static power during the OC phase due to the transistors operating in the saturation region. In addition, the previous offset-canceling techniques have to precede charge sharing, resulting in additional timing overhead. Furthermore, the previous BLSAs suffer from a large area due to two capacitors, high sensitivity to ambient noise, and imbalanced sensing problems, which impedes them from being utilized for the highly scaled DRAM process. This article proposes a dual-input stacked inverter-based single-ended sense amplifier (DISA) to achieve improved sensing capability with reduced energy consumption, small area, and high speed. The dual-input stacked inverter in DISA significantly reduces the static current during both OC and main sensing phases while improving inverter gain. In addition, DISA achieves the smallest area compared to the previous BLSAs because of the use of a single capacitor in the single-ended structure. The simultaneous offset canceling and charge sharing also contribute to the fast sensing operation of DISA. According to the measurement on the experimental chip fabricated in a 28-nm CMOS technology, DISA achieves the shortest sensing time of <9> $V_{\text {DD}}$ .