A Compact 20–24-GHz Sub-Sampling PLL With Charge-Domain Bandwidth Control Scheme

Abstract

This article introduces a compact 20–24-GHz integer-N dual-path sub-sampling phase-locked loop (DPSSPLL) with a charge-domain bandwidth control scheme. By leveraging the differential configuration of the type-I path, a charge-neutralization-based switched-capacitor gain control circuit is proposed to effectively optimize the phase-locked loop (PLL) loop bandwidth. Different from conventional approaches that use slope-controlled circuits or charge pumps, the proposed method achieves a wide control range with minimal in-band phase noise (PN) contribution. Rigorous analysis is introduced to accurately predict the frequency response and noise contribution of the proposed topology. The proportional-integral dual-path (DP) architecture, combined with an inductor-less true single-phase clock (TSPC) divider in the feedback path, enables a compact implementation. Fabricated using a 40-nm CMOS process, the prototype demonstrates an integrated jitter of 61.23 fs at 22 GHz from 1 kHz to 100 MHz, accompanied by a figure of merit (FoM) of −253.0 dB and a small core area of 0.057 mm2. The measurement results validate the effectiveness of the proposed gain and bandwidth control scheme.