A PEEC-Based Fast Direct Solver for Interconnect L&R Extraction

Abstract

A fast direct solver based on the partial element equivalent circuit is proposed for extracting the parasitic inductance and resistance of high-speed interconnects in free space. By adopting the magnetoquasistatic assumption, an equivalent circuit model for thin conductors is first constructed, where the negligible displacement current is eliminated. To lower computation costs, the mesh analysis method is then introduced to transform the system matrix of the modified nodal analysis into a compact formulation. Consequently, a hierarchically off-diagonal low-rank matrix format is applied to the resulting matrix for efficient compression and inversion. A sorting strategy is also developed to address the compression challenges posed by multiple zero matrix elements, a common occurrence due to the geometric characteristics of interconnects. The proposed method offers a solution for large and multiport interconnect problems with high accuracy, enhanced efficiency, and reduced memory requirements.