The Effect of Gate Drive Resistance on the CM EMI Performance of the Balanced Inverter With Asymmetrical Parasitic Impedance Distribution

Abstract

This paper presents an investigation of the effects of the gate drive resistance on the performance of the balanced inverter used for common-mode voltage cancellation. A simplified analytical common-mode voltage model that incorporates the circuit stray inductances is derived to capture the impact of the gate drive resistance on the effectiveness of common-mode voltage cancellation during switching transients. Experiments with different gate drive resistance have been implemented to evaluate the proposed analytical model on a 30-kW hardware demonstrator unit. The experimental results show raising the gate resistance from 4 Ω to 8 Ω reduces the peak value of the source common-mode voltage frequency spectrum by approx. 6 dB, and the inverter power loss increases by approx. 54%, highlighting the performance tradeoffs associated with this technique.