A 22.8–26.0-GHz VCO With Discriminative-Harmonic-Current-Manipulating for Phase Noise Improvement

IF 5.6 1区 工程技术 Q1 ENGINEERING, ELECTRICAL & ELECTRONIC IEEE Journal of Solid-state Circuits Pub Date : 2024-11-19 DOI:10.1109/JSSC.2024.3494236
Zehui Kang;Changwenquan Song;Liang Wu
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Abstract

A discriminative-harmonic-current-manipulating (DHCM) technique is proposed to improve the phase noise (PN) of high-frequency voltage-controlled oscillators (VCOs). Superior PN performance has been demonstrated by conventional multi-resonance VCOs when they are equipped with appropriately tailored tank impedance. However, meticulous alignment of the impedance peaks is typically required through manual tuning, particularly at high frequencies. In this work, the 3rd harmonic voltage, crucial for reshaping the impulse sensitivity function (ISF), is sustained by substantially boosting the 3rd harmonic current. Meanwhile, the 2nd harmonic current, identified as causing high ISF sensitivity and consequent noticeable PN fluctuations, is drastically suppressed. By selectively manipulating these harmonic currents, the rigorous requirement on the concurrent multiple impedance peaks is alleviated, thereby enabling a tuning-free multi-resonance oscillation. The DHCM VCO prototyped in a 65-nm CMOS process measures a tuning range of 22.8–26 GHz and PN of −134.6 dBc/Hz at 10-MHz offset, while consuming dc power of 7.3–9.7 mW from a 0.6-V supply. The figure-of-merit (FoM) and FoM with tuning range ( ${\mathrm {FoM}}_{T}$ ) achieved are up to 193.8 and 196.3 dBc/Hz, respectively. The core area occupied is 0.12 mm2.
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一种具有鉴别性谐波电流操纵功能的 22.8-26.0 GHz VCO,可改善相位噪声
针对高频压控振荡器(vco)的相位噪声问题,提出了一种判别谐波电流操纵(DHCM)技术。传统的多共振vco在配备合适的槽阻抗时,具有优越的PN性能。但是,通常需要通过手动调谐对阻抗峰值进行细致的校准,特别是在高频时。在这项工作中,对重塑脉冲灵敏度函数(ISF)至关重要的三次谐波电压是通过大幅提高三次谐波电流来维持的。同时,导致高ISF灵敏度和随之而来的明显PN波动的二次谐波电流被大幅抑制。通过选择性地操纵这些谐波电流,减轻了对并发多个阻抗峰值的严格要求,从而实现了无需调谐的多谐振振荡。采用65纳米CMOS工艺的DHCM VCO在10 mhz偏置时的调谐范围为22.8-26 GHz, PN为- 134.6 dBc/Hz,同时从0.6 v电源消耗7.3-9.7 mW的直流功率。在调谐范围(${\ mathm {FoM}}_{T}$)下实现的性能因数(FoM)和FoM分别高达193.8和196.3 dBc/Hz。核心占地面积0.12 mm2。
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来源期刊
IEEE Journal of Solid-state Circuits
IEEE Journal of Solid-state Circuits 工程技术-工程:电子与电气
CiteScore
11.00
自引率
20.40%
发文量
351
审稿时长
3-6 weeks
期刊介绍: The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuits modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.
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