A 26.5–29.5-GHz Current-Reused Low Noise Amplifier With Optimized Gate Bias and Flat-Gain Matching Techniques for 5G Communication

Abstract

This paper presents a Ka-band flat-gain low-noise amplifier (LNA) in 65-nm CMOS technology. An optimized gate bias technique is utilized for comprehensive optimization among noise figure (NF), input 1 dB compression point (IP_1dB), and power consumption. Then a current-reused technique is used to further reduce power consumption, and an inductor is inserted in the current-reused DC path to improve the circuit's common mode stability. The interstage and output magnetic-coupled resonator (MCR) matching network with individual pole manipulation is optimized to achieve an enhanced gain flatness. From the measurement results, S21 of 14.8–15.5 dB is achieved from 26.5 to 29.5 GHz, with a gain ripple of 0.7 dB. Measured NF varies from 2.85 to 3.3 dB, with the lowest NF at 27.5 GHz. The measured IP_1dB at 28 GHz has achieved as high as −12.5 dBm. The whole LNA consumes 6.8 mW under a 1-V supply, achieving a high FoM of 25.31 Hz in dB (dBHz). The fabricated LNA occupies a core area of 0.1 mm².