A novel low complexity, low latency rate 1/2 FEC code

Maan A.S. Al-Adwany, Mohammed H. Al-Jammas, Hind Th. Hamdoon
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Abstract

In this paper, a relatively simple and low complexity rate 1/2 FEC (Forward Error Correction) code has been proposed. The proposed encoder combines the effect of the low cross correlation of two orthogonal sequences along with the effect of the quadrature phase to achieve the desired performance. A mathematical modeling for the proposed code has been accomplished which indicates that the code is able to deliver a 3dB coding gain. The obtained results revealed that the performance of the proposed code is comparable to that of the Convolutional Codes (CCs). Interestingly, the latency analysis showed that, unlike polar codes and convolutional codes where latency is correlated with the data block size or traceback depth (TB), the proposed code exhibits a decoding latency of a single clock cycle. Furthermore, the proposed code and the CC have been implemented on an Field Programmable Gate Array (FPGA) platform to evaluate the overhead in terms of usability of hardware resources. The experimental results showed that the proposed code can achieve a 3dB coding gain, which is in agreement with the outcomes of the mathematical analyses. Moreover, the proposed code showed relatively fewer usability of hardware resources. Accordingly, the proposed code is suitable for applications that require a good balance between error correction and data rate.
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一种新颖的低复杂度,低延迟率1/2 FEC代码
本文提出了一种相对简单且复杂度较低的1/2前向纠错码。该编码器结合了两个正交序列的低互相关效应和正交相位效应,达到了理想的性能。对所提出的代码进行了数学建模,表明该代码能够提供3dB的编码增益。实验结果表明,该编码的性能与卷积编码相当。有趣的是,延迟分析表明,与延迟与数据块大小或回溯深度(TB)相关的极性码和卷积码不同,所提出的代码显示出单个时钟周期的解码延迟。此外,所提出的代码和CC已在现场可编程门阵列(FPGA)平台上实现,以评估硬件资源可用性方面的开销。实验结果表明,该编码可实现3dB的编码增益,与数学分析结果一致。此外,所建议的代码显示出相对较少的硬件资源可用性。因此,建议的代码适用于需要在纠错和数据速率之间取得良好平衡的应用程序。
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