Maan A.S. Al-Adwany, Mohammed H. Al-Jammas, Hind Th. Hamdoon
{"title":"A novel low complexity, low latency rate 1/2 FEC code","authors":"Maan A.S. Al-Adwany, Mohammed H. Al-Jammas, Hind Th. Hamdoon","doi":"10.1016/j.prime.2024.100838","DOIUrl":null,"url":null,"abstract":"<div><div>In this paper, a relatively simple and low complexity rate <span><math><mrow><mn>1</mn><mo>/</mo><mn>2</mn></mrow></math></span> FEC (Forward Error Correction) code has been proposed. The proposed encoder combines the effect of the low cross correlation of two orthogonal sequences along with the effect of the quadrature phase to achieve the desired performance. A mathematical modeling for the proposed code has been accomplished which indicates that the code is able to deliver a <span><math><mrow><mtext>3</mtext><mspace></mspace><mtext>dB</mtext></mrow></math></span> coding gain. The obtained results revealed that the performance of the proposed code is comparable to that of the Convolutional Codes (CCs). Interestingly, the latency analysis showed that, unlike polar codes and convolutional codes where latency is correlated with the data block size or traceback depth (<span><math><mi>TB</mi></math></span>), the proposed code exhibits a decoding latency of a single clock cycle. Furthermore, the proposed code and the CC have been implemented on an Field Programmable Gate Array (FPGA) platform to evaluate the overhead in terms of usability of hardware resources. The experimental results showed that the proposed code can achieve a <span><math><mrow><mtext>3</mtext><mspace></mspace><mtext>dB</mtext></mrow></math></span> coding gain, which is in agreement with the outcomes of the mathematical analyses. Moreover, the proposed code showed relatively fewer usability of hardware resources. Accordingly, the proposed code is suitable for applications that require a good balance between error correction and data rate.</div></div>","PeriodicalId":100488,"journal":{"name":"e-Prime - Advances in Electrical Engineering, Electronics and Energy","volume":"10 ","pages":"Article 100838"},"PeriodicalIF":0.0000,"publicationDate":"2024-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"e-Prime - Advances in Electrical Engineering, Electronics and Energy","FirstCategoryId":"1085","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S2772671124004182","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
In this paper, a relatively simple and low complexity rate FEC (Forward Error Correction) code has been proposed. The proposed encoder combines the effect of the low cross correlation of two orthogonal sequences along with the effect of the quadrature phase to achieve the desired performance. A mathematical modeling for the proposed code has been accomplished which indicates that the code is able to deliver a coding gain. The obtained results revealed that the performance of the proposed code is comparable to that of the Convolutional Codes (CCs). Interestingly, the latency analysis showed that, unlike polar codes and convolutional codes where latency is correlated with the data block size or traceback depth (), the proposed code exhibits a decoding latency of a single clock cycle. Furthermore, the proposed code and the CC have been implemented on an Field Programmable Gate Array (FPGA) platform to evaluate the overhead in terms of usability of hardware resources. The experimental results showed that the proposed code can achieve a coding gain, which is in agreement with the outcomes of the mathematical analyses. Moreover, the proposed code showed relatively fewer usability of hardware resources. Accordingly, the proposed code is suitable for applications that require a good balance between error correction and data rate.