Bumjun Kim;Seonghyeok Park;Su-Hyun Han;Jung-Hoon Chun;Jaehyuk Choi;Seong-Jin Kim
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引用次数: 0
Abstract
This article presents a solid-state flash light detection and ranging (LiDAR) sensor with an in-pixel zoom histogramming time-to-digital converter (hTDC). The proposed zoom hTDC combines two different conversion techniques such as the direct time-of-flight (ToF) and indirect ToF (iToF), realizing a two-step coarse-fine TDC architecture based on a single 10-b histogramming-bit (Hb) time-gated event/linear up-down counter (UDC). A 6-b time-bit (Tb) coarse TDC is implemented with a successive approximation (SA) algorithm in that the ToF value is found out by the binary search manner, dramatically reducing the number of memories from $2{^{T_{\text {b}}} \times \text { H}_{\text {b}}}$ to ${T_{\text {b}}} {+}$ Hb. The UDC is utilized for counting the single-photon avalanche diode (SPAD) events for calculating the histogram in the coarse SA-hTDC mode, while it is reconfigured to the up-counter for estimating the phase difference which is taken by a ratio of linear counts between adjacent coarse bins in the fine iToF mode. Fabricated in a 110-nm CIS process, the prototype flash LiDAR sensor with a $100{\times } 76$ pixel array demonstrates a 20-fps depth imaging acquisition in indoor environments. A 10-fps depth imaging at outdoor environments up to 10-m range consumes 154.5 mW. The maximum detectable range of 50 m is measured, and the depth resolutions of both to-digital converters (TDCs) are given by 150 and 9 cm, respectively, under an infrared (IR) emitter with a peak power of 75 W and a duty cycle of 0.08%.
期刊介绍:
The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuits modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.