High-Efficiency Ultrasound Energy Harvesting Interface With Auto-Calibrated Timing Control From −25 °C to 85 °C

IF 5.6 1区 工程技术 Q1 ENGINEERING, ELECTRICAL & ELECTRONIC IEEE Journal of Solid-state Circuits Pub Date : 2024-12-04 DOI:10.1109/JSSC.2024.3506781
Guangshu Zhao;Chao Xie;Chenxi Wang;Milin Zhang;Man-Kay Law
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Abstract

This work presents a high-efficiency ultrasound energy harvesting interface with auto-calibrated timing control, featuring: 1) the proposed $C_{\text {P}}$ auto-calibration, consisting of the half bias-flip time ( $t_{\text {half}}$ ) detection and adaptive closed-loop time calibration (ACTC) to improve the system’s robustness against piezoelectric transducer (PZT) materials and environmental variations; 2) the proposed charge recycling (CR) bootstrapping driver to reduce conduction loss and improve the $C_{\text {P}}$ auto-calibration accuracy as well as the peak voltage flipping efficiency ( $\eta _{\text {flip}}$ ); and 3) the proposed coarse detection and fine calibration technique to eliminate the inherent timing offset and increase the acceptable input excitation frequency range. The fabricated chip prototype in 0.18- $\mu $ m silicon on insulator (SOI) CMOS process can adapt to both PZT5A (nominal ${C_{\text {P}}}~{\sim }~114$ pF) and PZT5H (nominal ${C_{\text {P}}}~{\sim }~190$ pF) and is capable of operating over a wide temperature range from ${-} 25~{^{\circ }}$ C to $85~{^{\circ }}$ C. The proposed $C_{\text {P}}$ auto-calibration and CR bootstrapping driver can improve the $\eta _{\text {flip}}$ to as high as 93.6% at an output power of $496.6~{\mu }$ W. With the proposed coarse detection and fine calibration technique, this work demonstrates a high measured peak power conversion efficiency (PCE) of 94.5%, corresponding to a ~23% improvement when compared with the prior ultrasound energy harvesting interface while achieving a favorable figure of merit (FoM) of $8.13{\times }$ .
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从$-$25 $^{\circ}$C到$ 85 $^{\circ}$C,具有自动校准定时控制的高效超声能量收集接口
本文提出了一种具有自动校准定时控制的高效超声能量收集接口,具有以下特点:1)提出的$C_{\text {P}}$自动校准,包括半偏置翻转时间($t_{\text {half}}$)检测和自适应闭环时间校准(ACTC),以提高系统对压电换能器(PZT)材料和环境变化的鲁棒性;2)提出电荷回收(CR)自举驱动器,降低导通损耗,提高$C_{\text {P}}$自校准精度和峰值电压翻转效率($\eta _{\text {flip}}$);3)提出了粗检测和精细校准技术,消除了固有的时序偏移,增加了可接受的输入激励频率范围。在0.18- $\mu $ m绝缘体上硅(SOI) CMOS工艺中制作的芯片原型可以适应PZT5A(标称${C_{\text {P}}}~{\sim }~114$ pF)和PZT5H(标称${C_{\text {P}}}~{\sim }~190$ pF),并且能够在${-} 25~{^{\circ }}$ C到$85~{^{\circ }}$ C的宽温度范围内工作。提出的$C_{\text {P}}$自动校准和CR引导驱动可以将$\eta _{\text {flip}}$提高到高达93.6% at an output power of $496.6~{\mu }$ W. With the proposed coarse detection and fine calibration technique, this work demonstrates a high measured peak power conversion efficiency (PCE) of 94.5%, corresponding to a ~23% improvement when compared with the prior ultrasound energy harvesting interface while achieving a favorable figure of merit (FoM) of $8.13{\times }$ .
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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来源期刊
IEEE Journal of Solid-state Circuits
IEEE Journal of Solid-state Circuits 工程技术-工程:电子与电气
CiteScore
11.00
自引率
20.40%
发文量
351
审稿时长
3-6 weeks
期刊介绍: The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuits modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.
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