A Compact 180-GHz Stacked-FET Oscillator With 11-dBm Output Power and 13.9% DC-to-RF Efficiency in a 45-nm CMOS SOI Process

Abstract

We present an oscillator design based on stacked-FET for high-power terahertz (THz) signal generation in CMOS technologies. This design addresses the challenges commonly encountered in conventional high-power oscillators. These challenges include a low inductor quality factor (Q) associated with the use of large active devices and the need for extensive chip area when combining multiple optimally designed cells. Based on a $\Pi $ -embedded oscillator architecture, we show that with N-stacked FET, the optimal embedding inductor and load resistance increase approximately with N. This contrasts with the traditional size scaling approach, where L and R decrease unfavorably as the device size increases. We take advantage of this characteristic by proposing a design methodology that simultaneously achieves high output power and optimal inductor Q. The concept is validated by a design example of a two-stack $\Pi $ -embedded oscillator. Fabricated using the 45-nm CMOS SOI process to eliminate body effects and minimize substrate loss, two losslessly combined oscillator cores deliver a total RF power of 11 dBm at 180 GHz. Without the use of varactors, this design achieves the highest output power among CMOS oscillators at this frequency, making it suitable for narrowband applications.