BEE-SLAM: A 65-nm 17.96-TOPS/W Location-Sharing-Based Multi-Agent Neuromorphic SLAM Accelerator for Swarm Robotics

IF 5.6 1区 工程技术 Q1 ENGINEERING, ELECTRICAL & ELECTRONIC IEEE Journal of Solid-state Circuits Pub Date : 2024-12-09 DOI:10.1109/JSSC.2024.3505960
Jaehyun Lee;Dong-Gu Choi;Gain Kim;Minyoung Song;Jong-Hyeok Yoon
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Abstract

Multi-agent (MA) simultaneous localization and mapping (SLAM) has been rigorously explored to enhance map accuracy in swarm robotics. Although centralized MA SLAM systems, which depend on a server for complex computations in map optimization, have been extensively studied, the circuit-domain approaches to decentralized MA SLAM systems are still limited due to challenges such as limited memory capacity and security vulnerabilities in wireless inter-agent data transmission. Thus, we propose a BEE-SLAM accelerator, a location-sharing MA neuromorphic SLAM accelerator inspired by bee communication for decentralized MA SLAM systems. The location-sharing-based MA error correction (MAEC) is employed to attain accurate map results without loop closure with a 94.81% reduced number of operations compared to the global map-based MA SLAM. In addition, a $7 {\times } 7$ pulsewidth modulation (PWM)-based hybrid mixed-signal/digital pose-cell (HY-PC) array with pseudo pose cells (PPCs) achieves $2.04{\times }$ energy efficiency compared to the oscillatory pose-cell array. The test chip fabricated in a 65-nm CMOS technology achieves a peak energy efficiency of 17.96 TOPS/W under $350 {\times } 450$ m outdoor exploration.
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蜂群机器人基于位置共享的65nm 17.96 tops /W多智能体神经形态SLAM加速器BEE-SLAM
为了提高群机器人的地图精度,对多智能体(MA)同步定位和地图绘制(SLAM)进行了深入的研究。虽然集中式maslam系统依赖于服务器进行复杂的地图优化计算,已经得到了广泛的研究,但由于有限的内存容量和无线代理间数据传输的安全漏洞等挑战,分散式maslam系统的电路域方法仍然受到限制。因此,我们提出了一个bee -SLAM加速器,一个受蜜蜂通信启发的位置共享MA神经形态SLAM加速器,用于分散的MA SLAM系统。采用基于位置共享的MA误差校正(MAEC),在不闭合环路的情况下获得准确的地图结果,与基于全局地图的MA SLAM相比,减少了94.81%的操作次数。此外,与振荡式位元阵列相比,基于7 {\times} 7$脉宽调制(PWM)的混合混合信号/数字位元(hyc - pc)阵列具有2.04{\times}$的能量效率。采用65纳米CMOS技术制造的测试芯片在350美元的户外探测下达到了17.96 TOPS/W的峰值能效。
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来源期刊
IEEE Journal of Solid-state Circuits
IEEE Journal of Solid-state Circuits 工程技术-工程:电子与电气
CiteScore
11.00
自引率
20.40%
发文量
351
审稿时长
3-6 weeks
期刊介绍: The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuits modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.
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