An Inductive Loading Simultaneous Noise and Input Matching Technique With Current Reuse for Low-Power LNA

IF 5.6 1区 工程技术 Q1 ENGINEERING, ELECTRICAL & ELECTRONIC IEEE Journal of Solid-state Circuits Pub Date : 2024-12-11 DOI:10.1109/JSSC.2024.3511578
Phuoc B. T. Huynh;Gyeong-Seok Lee;Jun-Young Park;Tae-Yeoul Yun
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Abstract

This article presents an inductive loading simultaneous noise and input matching (ILSNIM) technique for a low-power low-noise amplifier (LNA). In contrast to conventional simultaneous noise and input matching (SNIM) methods, where lossy resistance associated with an on-chip low-Q gate inductor substantially degrades the total noise figure (NF) performance, the input stage of the proposed LNA exploits the gate-drain capacitance feedback incorporated with inductive loading for the first time to construct the input impedance network. This design approach overcomes the NF limitation in conventional SNIM techniques by eliminating the lossy gate inductor while boosting the transconductance to achieve SNIM under low power consumption. Furthermore, a current-reuse structure with a cascaded stage is applied not only to enhance the overall gain but also to generate a noiseless resistive component that addresses the instability issue without adverse impacts on other performances. Fabricated using a 0.11- $\mu $ m complementary metal-oxide-semiconductor (CMOS) process, the proposed ILSNIM LNA demonstrates a gain of 13.6 dB, an NF of 2.8 dB, and a third-order input intercept point (IIP3) of -5.2 dBm at 6.8 GHz under a 1.2-mW power dissipation from a 1-V supply.
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基于电流复用的低功率LNA电感负载同步噪声与输入匹配技术
提出了一种用于低功耗低噪声放大器的感应负载同步噪声与输入匹配技术。传统的同时噪声和输入匹配(SNIM)方法中,与片上低q门电感相关的有损电阻大大降低了总噪声系数(NF)性能,与之相反,所提出的LNA的输入级首次利用结合电感负载的门-漏电容反馈来构建输入阻抗网络。该设计方法克服了传统SNIM技术的NF限制,消除了损耗门电感,同时提高了跨导性,从而在低功耗下实现了SNIM。此外,采用级联级的电流复用结构不仅可以提高总体增益,还可以产生无噪声的电阻元件,从而解决不稳定性问题,而不会对其他性能产生不利影响。采用0.11- $\mu $ m互补金属氧化物半导体(CMOS)工艺制造的ILSNIM LNA在1 v电源1.2 mw功耗下,在6.8 GHz下的增益为13.6 dB, NF为2.8 dB,三阶输入截距点(IIP3)为-5.2 dBm。
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来源期刊
IEEE Journal of Solid-state Circuits
IEEE Journal of Solid-state Circuits 工程技术-工程:电子与电气
CiteScore
11.00
自引率
20.40%
发文量
351
审稿时长
3-6 weeks
期刊介绍: The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuits modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.
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