{"title":"Class-G Impedance-Modulation Multi-Core Power Oscillator for High Pout and Power Back-Off Efficiency Enhancement","authors":"Yiyang Shu;Xun Luo","doi":"10.1109/JSSC.2024.3510417","DOIUrl":null,"url":null,"abstract":"Power oscillator is promising to directly generate the signal to the output with a high system efficiency. However, the peak output power and the efficiency at deep power back-off (PBO) are limited. In this article, the architecture of impedance-modulation multi-core power oscillator is proposed. The reconfigurable power-combining matching resonator is introduced and analyzed to obtain high efficiencies and low phase noise at peak and PBO states. Meanwhile, the output matching is investigated to maintain the high efficiency along with the tuning of oscillation frequency. To verify the mechanism, a dual-core power oscillator with Class-G supply switching is designed and fabricated in a 40-nm CMOS technology. The digitally controlled tail resistor array is used to tune the output power continuously. Measurements exhibit a 33% tuning range from 2.3 to 3.2 GHz. The peak output power is 10 dBm, while the efficiencies at 0-/3-/6-/9-dB PBOs are 39%, 37%, 33%, and 30%, respectively. The 1-MHz offset phase noise is −131.5 to −127.2 dBc/Hz over the operation frequency.","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"60 7","pages":"2511-2521"},"PeriodicalIF":5.6000,"publicationDate":"2024-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10794770","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Journal of Solid-state Circuits","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10794770/","RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q1","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
Power oscillator is promising to directly generate the signal to the output with a high system efficiency. However, the peak output power and the efficiency at deep power back-off (PBO) are limited. In this article, the architecture of impedance-modulation multi-core power oscillator is proposed. The reconfigurable power-combining matching resonator is introduced and analyzed to obtain high efficiencies and low phase noise at peak and PBO states. Meanwhile, the output matching is investigated to maintain the high efficiency along with the tuning of oscillation frequency. To verify the mechanism, a dual-core power oscillator with Class-G supply switching is designed and fabricated in a 40-nm CMOS technology. The digitally controlled tail resistor array is used to tune the output power continuously. Measurements exhibit a 33% tuning range from 2.3 to 3.2 GHz. The peak output power is 10 dBm, while the efficiencies at 0-/3-/6-/9-dB PBOs are 39%, 37%, 33%, and 30%, respectively. The 1-MHz offset phase noise is −131.5 to −127.2 dBc/Hz over the operation frequency.
期刊介绍:
The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuits modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.