Quantum Assertion Scheme for Assuring Qudit Robustness

IF 1.4 3区计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Computer Architecture Letters Pub Date : 2024-11-04 DOI:10.1109/LCA.2024.3483840

Navnil Choudhury;Chao Lu;Kanad Basu

引用次数: 0

Abstract

Noisy Intermediate-Scale Quantum (NISQ) computers are impeded by constraints such as limited qubit count and susceptibility to noise, hindering the progression towards fault-tolerant quantum computing for intricate and practical applications. To augment the computational capabilities of quantum computers, research is gravitating towards qudits featuring more than two energy levels. This paper presents the inaugural examination of the repercussions of errors in qudit circuits. Subsequently, we introduce an innovative qudit-based assertion framework aimed at automatically detecting and reporting errors and warnings during the quantum circuit design and compilation process. Our proposed framework, when subjected to evaluation on existing quantum computing platforms, can detect both new and existing bugs with up to 100% coverage of the bugs mentioned in this paper.

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确保 Qudit 稳健性的量子断言方案

有噪声的中等规模量子（NISQ）计算机受到诸如有限的量子比特数和对噪声的易感性等限制的阻碍，阻碍了向复杂和实际应用的容错量子计算的发展。为了增强量子计算机的计算能力，研究正趋向于具有两个以上能级的量子。本文提出了在量子电路误差的影响的初步检查。随后，我们引入了一个创新的基于量子比特的断言框架，旨在自动检测和报告量子电路设计和编译过程中的错误和警告。我们提出的框架在现有的量子计算平台上进行评估时，可以检测到新的和现有的错误，并且对本文提到的错误的覆盖率高达100%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-

CiteScore

4.60

自引率

4.30%

发文量

期刊介绍： IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.

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