A Fully Row/Column-Parallel MRAM in-Memory Computing Macro With Memory-Resistance Boosting and Weighted Multi-Column ADC Readout

Abstract

This work demonstrates a 256(row) ${\times } 512$ (col.) fully row/column-parallel in-memory computing (IMC) macro employing foundry MRAM in 22-nm FD-SOI CMOS. Embedded nonvolatile memory (eNVM) offers advantages in density, nonvolatility, and scalability in advanced technology nodes compared to SRAM, but incurs worse signal-to-noise ratio (SNR) challenges which restrict row parallelism and exacerbate readout overheads, thus limiting achievable IMC throughput and energy efficiency. The presented prototype enables high row parallelism, as well as high-sensitivity and power/area-efficient readout, via a cascode-based feedback architecture. The feedback architecture performs linear conductance-to-current conversion, which enables signal weighting and summation to feed a single multi-column ADC. The ADC employs a conductance-feedback SAR architecture to achieve a high resolution of 6 b. The prototype demonstrates compute density of 5.5 1b-TOPS/mm2 and energy efficiency of 19.5-41.6 1b-TOPS/W, using an unmodified foundry bit-cell and memory array. Operation is verified with a six-layer VGG-style convolutional neural network (NN), achieving 90.25% accuracy on CIFAR-10, and 71.08% on CIFAR-100, both equivalent to ideal software accuracy.