A Harmonic-Mixer-Based Fractional-N PLL Employing Voltage-Domain Feed-Forward Noise Cancellation

Abstract

A harmonic-mixer (HM)-based fractional-N phase-locked loop (PLL) employing voltage-domain feed-forward noise cancellation (FFNC) is presented in this article. By adding the output of the first-stage phase detector (PD) to that of the second-stage PD, the noise and power overhead from the first-stage voltage-controlled oscillator (VCO) can be suppressed, without relying on blocks such as high-speed delay lines that need to operate with a much higher bandwidth than the noise component that is being canceled. Architectural choices are made to mitigate the effect of process variation on the noise cancellation to avoid the need for calibration. A proof-of-concept prototype is implemented in 65-nm CMOS technology that achieves 106-fs rms jitter and −63-dBc worst case fractional spur, and the phase noise (PN) improvement due to the proposed noise cancellation technique is demonstrated through measurement results.