A 0.38-mW 200-kHz-BW Digital-Intensive Single-Opamp Fourth-Order Continuous-Time Delta-Sigma Modulator With Third-Order Digital Noise Coupling in 28-nm CMOS

Abstract

This article presents a digital-intensive, single-opamp, 4th-order continuous-time delta-sigma modulator (CT DSM) architecture with a simple and low-power 3rd-order digital noise-coupling (DNC) assisted by a successive approximation register (SAR). To address the limited maximum stable amplitude (MSA) issue in high-order noise coupling, a digital back-end integrator is adopted to suppress the large input signal at the quantizer’s input, achieving an MSA of −1.6 dBFS even with aggressive noise shaping in a single-loop design. A digital adder-free 3rd-order DNC filter is introduced, which performs the addition directly in the charge domain using the capacitor digital-to-analog converter (DAC) in the SAR quantizer. Fabricated in 28-nm CMOS, the prototype demonstrates that a high-order CT DSM can be realized with a reduced analog burden by shifting most of the signal processing of the loop filter (LF) to the digital domain. It achieves a peak signal-to-noise and distortion ratio (SNDR), signal-to-noise ratio (SNR), and dynamic range (DR) of 89.0, 89.2, and 92.1 dB, respectively, across a 200-kHz bandwidth while consuming only 0.38 mW from a 1.1-V supply. The Schreier figure of merit (FoM) is 179.3 dB, and the Walden FoM is 41.2 fJ/conv.-step.