CRFF: A Static Contention-Free 23T Flip-Flop With Three Clock Load Transistors for Ultra-Low-Power Applications

Abstract

This article presents an ultra-low-power D flip-flop (FF) named clock-load reduced FF (CRFF), which employs 23 transistors with only three clock load transistors to support fully static, contention-free, and redundancy-free operations in a wide-supply-voltage range. In particular, to reduce the clock load, logic replacement is performed on clock-insensitive transistors. Moreover, a novel conditional charge scheme is adopted in internal clock signal (CKB), with which functionally identical transistors are merged and redundant transistors are removed for dynamic power and hardware overhead reduction. Finally, the presented CRFF and prior works are prototyped with a 22-nm ULL CMOS technology. Compared to the state-of-the-art low power FFs, the CRFF achieves the minimal clock loads, and measurement results show that the total power of the CRFF with 10% data activity is reduced from 48.8% to 17.0% at 0.9 V and 39.9% to 13.6% at 0.4 V, respectively. As a result, the CRFF is a prospective FF cell for the Internet-of-Things (IoT) and wearable computing scenarios.