A 5-nm 60-GS/s 7b 64-Way Time Interleaved Partial Loop Unrolled SAR ADC Achieving 35.2dB SNDR up to 32 GHz

Abstract

A 60-GS/s 7b 64-way time interleaved (TI) analog-to-digital converter (ADC) with analog front end (AFE) is described. The presented converter features a non-binary partial loop unrolled (LU) SAR SubADC architecture that leverages multiple comparators, thus enabling better tradeoff between noise and power compared to conventional SAR. Offsets mismatches among comparators of each SubADC are calibrated in background by detecting patterns in the SAR output decisions. This results in no need for any analog hardware reconfigurability or additional phase overhead. Fabricated in 5-nm technology, the prototype AFE and ADC deliver 35.5 and 35.2dB signal to noise and distortion ratio (SNDR) till 20 and 32 GHz, respectively, and draw 109.3 mW from 0.9 V supply.