Electra: Eliminating the Ineffectual Computations on Bitmap Compressed Matrices

IF 1.4 3区 计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Computer Architecture Letters Pub Date : 2024-12-12 DOI:10.1109/LCA.2024.3516057
Chaithanya Krishna Vadlamudi;Bahar Asgari
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Abstract

The primary computations in several applications, such as deep learning recommendation models, graph neural networks, and scientific computing, involve sparse matrix sparse matrix multiplications (SpMSpM). Unlike standard multiplications, SpMSpMs introduce ineffective computations that can negatively impact performance. While several accelerators have been proposed to execute SpMSpM more efficiently, they often incur additional overhead in identifying the effectual arithmetic computations. To solve this issue, we propose Electra, a novel approach designed to reduce ineffectual computations in bitmap-compressed matrices. Electra achieves this by i) performing logical operations on the bitmap data to know whether the arithmetic computation has a zero or non-zero value, and ii) implementing finer granular scheduling of non-zero elements to arithmetic units. Our evaluations suggest that on average, Electra achieves a speedup of 1.27× over the state-of-the-art SpMSpM accelerator with a small area overhead of 64.92 $\text{mm}^{2}$ based on 45 nm process.
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消除位图压缩矩阵的无效计算
在深度学习推荐模型、图神经网络和科学计算等应用中,主要的计算涉及稀疏矩阵稀疏矩阵乘法(SpMSpM)。与标准乘法不同,spmspm引入了可能对性能产生负面影响的无效计算。虽然已经提出了一些加速器来更有效地执行SpMSpM,但它们通常会在识别有效的算术计算时产生额外的开销。为了解决这个问题,我们提出了Electra,一种新颖的方法,旨在减少位图压缩矩阵中的无效计算。Electra通过以下方式实现了这一点:1)对位图数据执行逻辑操作,以了解算术计算是否具有零值或非零值;2)实现更精细的非零元素到算术单元的粒度调度。我们的评估表明,平均而言,Electra比最先进的SpMSpM加速器实现了1.27倍的加速,而基于45纳米工艺的面积开销仅为64.92 $\text{mm}^{2}$。
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来源期刊
IEEE Computer Architecture Letters
IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-
CiteScore
4.60
自引率
4.30%
发文量
29
期刊介绍: IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.
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