Cost-Optimized and Highly Robust Latches Providing Complete Quadruple-Node-Upset Tolerance and Recovery With Algorithm-Based Verifications

Abstract

With the aggressive shrinking of transistor feature sizes, nanoscale complementary metal oxide semiconductor (CMOS) circuits are becoming more vulnerable to multinode upsets, e.g., triple-node upsets as well as quadruple-node upsets (QNUs), caused by the effects of harsh radiation. This article first presents a QNU completely tolerant latch based on the so-called triple-path dual-interlocked cell (TPDICE) and the soft-error-interception module, namely quadruple-node-upset hardened latch (QNUHL). We further propose an advanced latch, namely quadruple-node-upset recovery hardened latch (QNURHL), which mainly employs 24 interlocked C-elements, to provide complete QNU recovery. Simulations based on the HSPICE tool demonstrate the complete QNU tolerance as well as the reasonable overhead for the QNUHL latch and also show that the QNURHL latch is recoverable from any possible QNU and can roughly save silicon area by 11% and power dissipation by 16%, compared with the QNU hardened latch of the same type. Moreover, an algorithm-based method for the verification of error tolerance and recovery of latches is proposed. The proposed method can simplify the verifications to demonstrate the capability of node-upset tolerance and/or recovery for latches.