A 0.5-V 125-MHz 256-Kb 22-nm SRAM With 10-aJ/bit Active Energy and 10-pW/bit Shutdown Power

Abstract

Conventional low-voltage (LV) static random access memories (SRAMs) utilizing separate read-and-write assist circuits sacrifice access speed too much, leading to poor energy efficiency. Overlaying additional assist circuits to enable power-saving modes can exacerbate speed loss and energy inefficiency. This work proposes a coordinated read-write-hold-retention-shutdown (SD) assist circuit design for SRAMs to improve speed at low VDD and reduce leakage current in active and power-saving modes. This leads to overall power reduction and enhanced energy efficiency. The implemented 22-nm 256-Kb SRAM can operate down to 0.45 V, with the minimum energy point at 0.5 V. At 0.5 V, TT corner, and $25~{^{\circ }}$ C, the measured maximum frequency ( $f_{\max }$ ) is 125 MHz with a 10 aJ/bit active energy, representing a 6.25 higher frequency with a 91% energy reduction, compared to the state-of-the-art 0.5-V SRAM in 28-nm bulk CMOS. The SRAM has a 12 pW/bit deep-sleep power and a 10 pW/bit SD power at 0.5 V.