A Multi-Event, 7.9-ps Resolution Time Amplification-Based TDC With an Ultra-Low Static Phase Error DLL Using Interpolator Recycling Technique for dToF Applications

Abstract

In this article, a multi-event time-to-digital converter (TDC) with a high conversion rate using an interpolator recycling technique is proposed. The conversion dead time is greatly reduced by reusing the coarse interpolation channel (CIC) during the quantization of Start and Stop signals. A high resolution is achieved by a coarse-fine interpolation with a calibration-free high-linearity time amplifier (TA). A flash sub-TDC using a novel fully symmetric quantization (FSQ) scheme is proposed to implement fine interpolation, which helps improve the linearity. An ultra-low static phase error (SPE) DLL with time amplification in the feedback loop is proposed, to improve the TDC’s precision and linearity. The proposed TDC is fabricated in a 0.18- $\mu $ m CMOS technology, achieving a 7.9-ps resolution over a 2033.5-ns dynamic range with a conversion rate of 80 MS/s. The worst case DNL and INL are +0.15/−0.09 LSB and +0.69/−0.43 LSB, respectively.