Novel Trade-offs in 5 nm FinFET SRAM Arrays at Extremely Low Temperatures

Abstract

Complementary metal–oxide–semiconductor (CMOS)-based computing promises drastic improvement in performance at extremely low temperatures (e.g., 77 K, 10 K). The field of extremely low temperature CMOS-environment-based computing holds the promise of delivering remarkable enhancements in both performance and power consumption. Static random access memory (SRAM) plays a major role in determining the performance and efficiency of any processor due to its superior performance and density. This work aims to reveal how extremely low temperature operations profoundly impact the existing well-known tradeoffs in SRAM-based memory arrays. To accomplish this, first, we measure and model the 5 nm fin field-effect transistors characteristics over a wide temperature range from 300 K down to 10 K. Next, we develop a framework to perform simulations on the SRAM array by varying the number of rows and columns for examining the influence of leakage current ($I$_leak) and parasitic effects of bit line (BL) and word line (WL) on the size and performance of the SRAM array under extremely low temperatures. For a comprehensive analysis, we further investigated the maximum attainable array size, extending our study down to 10 K, utilizing three distinct cell types. With the help of SRAM array simulations, we reveal that the maximum array size at extremely low temperatures is limited by WL parasitics instead of $I$_leak, and the performance of the SRAM is governed by BL and WL parasitics. In addition, we elucidate the influence of transistor threshold voltage ($V$_TH) engineering on the optimization of the SRAM array at extremely low temperature environments.