Characterization and Analysis of the 3D Gaussian Splatting Rendering Pipeline

IF 1.4 3区计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Computer Architecture Letters Pub Date : 2024-11-21 DOI:10.1109/LCA.2024.3504579

Jiwon Lee;Yunjae Lee;Youngeun Kwon;Minsoo Rhu

引用次数: 0

Abstract

Novel view synthesis, a task generating a 2D image frame from a specific viewpoint within a 3D object or scene, plays a crucial role in 3D rendering. Neural Radiance Field (NeRF) emerged as a prominent method for implementing novel view synthesis, but 3D Gaussian Splatting (3DGS) recently began to emerge as a viable alternative. Despite the tremendous interest from both academia and industry, there has been a lack of research to identify the computational bottlenecks of 3DGS, which is critical for its deployment in real-world products. In this work, we present a comprehensive end-to-end characterization of the 3DGS rendering pipeline, identifying the alpha blending stage within the tile-based rasterizer as causing a significant performance bottleneck. Based on our findings, we discuss several future research directions aiming to inspire continued exploration within this burgeoning application domain.

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三维高斯飞溅渲染管道的表征与分析

新颖视图合成是一种从3D对象或场景中的特定视点生成2D图像帧的任务，在3D渲染中起着至关重要的作用。神经辐射场（NeRF）是实现新视图合成的重要方法，但3D高斯飞溅（3DGS）最近开始成为一种可行的替代方法。尽管学术界和工业界对此都非常感兴趣，但目前还缺乏研究来确定3DGS的计算瓶颈，而这对于其在实际产品中的部署至关重要。在这项工作中，我们提出了3DGS渲染管道的全面端到端表征，确定了基于tile的光栅化器中的alpha混合阶段，这导致了显著的性能瓶颈。基于我们的发现，我们讨论了几个未来的研究方向，旨在激发在这个新兴应用领域的持续探索。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-

CiteScore

4.60

自引率

4.30%

发文量

期刊介绍： IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.

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