A 76.9 ppm/K Nano-Watt PVT-Insensitive CMOS Voltage Reference Operating From 4 to 300 K for Integrated Cryogenic Quantum Interface

Abstract

This work proposes a temperature and process-compensated low-power Cryo-CMOS voltage reference without trimming for quantum integrated interface, which is capable of operating continuously from room temperature (RT) down to cryogenic temperatures. By compensating for the main accuracy limiting factors including the process dependence of the transistor threshold voltage, device mismatch and device nonlinearity deterioration, the proposed fully CMOS voltage reference achieves simultaneous process and temperature compensation over an ultra-wide operating range from 300 to 4 K. Fabricated in a standard 180 nm process, measurement results from 80 test chips across two batches can successfully demonstrate an average temperature coefficient (TC) of 76.9 ppm/K after a one-time model correction. The proposed circuit consumes only 195–304 nW over the entire operating range and maintains a voltage fluctuation of just 0.72% with an average ${V} _{\mathrm {REF}}$ of 1.045 V. The minimum supply voltages are 1.5 V at 300 K and 1.9 V at 4 K, respectively. The proposed process voltage temperature (PVT)-insensitive highly accurate voltage reference in standard CMOS with nanowatt power consumption can be integrated cost-effectively into quantum interface circuits.