A 28-nm Software-Defined Accelerator Chip With Circuit-Pipeline Scaling and Intrinsic Physical Unclonable Function Enabling Secure Configuration

Abstract

As emerging applications raise ever-boosting and varying computational demand, the reconfigurable accelerator is becoming prevalent due to balanced performance, efficiency, and flexibility. Although the functions of its processing elements (PEs) and interconnections can be defined by a high-level software program, the circuit parameters are mostly managed by hardware or the compiler, leaving opportunities for in-depth optimization and novel features. Considering that the circuit adjustment is of great value in terms of low power and security, this article presents a novel software-defined accelerator named cross-domain software-defined chip (CDSDC), of which most chip properties including circuit parameters, logic, and pipelines can be programmed synergistically by software at runtime. With this design scheme, CDSDC provides new features including: 1) dynamic pipeline-voltage-frequency scaling (DPVFS), which combines pipeline reconfiguration with voltage-frequency scaling to generate an optimal chip configuration for various applications; 2) intrinsic physical unclonable function (PUF), which leverages the uniform PEs as measured circuit delay elements by adjusting the circuit parameters, extracting the entropy of manufacturing process variation, and taking response bits as a PUF; and 3) device-binding confidential configuration, which uses the intrinsic PUF and ASCON algorithm to encrypt/decrypt configuration. The CDSDC has been implemented in silicon as a 28-nm Taiwan Semiconductor Manufacturing Company (TSMC) HPC+ 1P8M 6-mm2 test chip, operating at peak 400 MHz and 0.9 V, achieving a peak energy efficiency of 51 GOPS/W. It improves performance and efficiency for cross-domain patterns of computation by DPVFS. It improves hardware security against reverse engineering attacks by using intrinsic PUF and device-specific encrypted configuration flow.