{"title":"NeuroFlare: An mm3-Scale Wireless Neural Interface Device With Simultaneous Neural Recording and Optical Stimulation","authors":"Linran Zhao;Yan Gong;Xiang Liu;Wei Shi;Yiming Han;Wen Li;Yaoyao Jia","doi":"10.1109/JSSC.2025.3532646","DOIUrl":null,"url":null,"abstract":"This article presents the creation of a wireless, miniature implantable opto-electro neural interface device called NeuroFlare, capable of simultaneous neural recording and optical stimulation. NeuroFlare features a low-power, dual-modal application-specific integrated circuit (ASIC) fabricated using the 180-nm CMOS process. To support the power-intensive optical stimulation in NeuroFlare, the ASIC employs a novel linear-charging switched-capacitor stimulation (LC-SCS) structure. The LC-SCS, operating under only a 1.2-V supply voltage, can illuminate the LED with a driving voltage three times the supply voltage and large current pulses of up to 12 mA while maintaining a high charging efficiency of 86.4%. In addition, LC -SCS requires only one off-chip capacitor, greatly facilitating device miniaturization. To accurately record neural signals in the presence of stimulation artifacts, the ASIC employs a delta-sigma modulator (<inline-formula> <tex-math>$\\Delta \\Sigma $ </tex-math></inline-formula>M)-based recording front end with a wide dynamic range (DR) to directly digitize the neural signals. The <inline-formula> <tex-math>$\\Delta \\Sigma $ </tex-math></inline-formula>M features a 2nd-order loop architecture implemented using a linearized transconductance-capacitor (Gm-C) integrator followed by an active noise-shaping (NS) successive approximation register (SAR) quantizer. The <inline-formula> <tex-math>$\\Delta \\Sigma $ </tex-math></inline-formula>M with a power consumption of <inline-formula> <tex-math>$9.8~{\\mu }$ </tex-math></inline-formula>W provides a peak DR of 83.7 dB, corresponding to a 400-mVPP linear input range. The <inline-formula> <tex-math>$\\Delta \\Sigma $ </tex-math></inline-formula>M’s 173.8-dB figure of merit (FoMDR) indicates its superior energy efficiency. The ASIC is assembled into a prototype of NeuroFlare measuring <inline-formula> <tex-math>$2.8 \\,\\, {\\times } \\,\\, 3.5 \\,\\, {\\times } \\,\\, 0.7$ </tex-math></inline-formula> mm3. The recorded light-evoked local field potential (LFP) verified the functionality of NeuroFlare in vivo.","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"60 9","pages":"3342-3354"},"PeriodicalIF":5.6000,"publicationDate":"2025-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Journal of Solid-state Circuits","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10856923/","RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q1","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
This article presents the creation of a wireless, miniature implantable opto-electro neural interface device called NeuroFlare, capable of simultaneous neural recording and optical stimulation. NeuroFlare features a low-power, dual-modal application-specific integrated circuit (ASIC) fabricated using the 180-nm CMOS process. To support the power-intensive optical stimulation in NeuroFlare, the ASIC employs a novel linear-charging switched-capacitor stimulation (LC-SCS) structure. The LC-SCS, operating under only a 1.2-V supply voltage, can illuminate the LED with a driving voltage three times the supply voltage and large current pulses of up to 12 mA while maintaining a high charging efficiency of 86.4%. In addition, LC -SCS requires only one off-chip capacitor, greatly facilitating device miniaturization. To accurately record neural signals in the presence of stimulation artifacts, the ASIC employs a delta-sigma modulator ($\Delta \Sigma $ M)-based recording front end with a wide dynamic range (DR) to directly digitize the neural signals. The $\Delta \Sigma $ M features a 2nd-order loop architecture implemented using a linearized transconductance-capacitor (Gm-C) integrator followed by an active noise-shaping (NS) successive approximation register (SAR) quantizer. The $\Delta \Sigma $ M with a power consumption of $9.8~{\mu }$ W provides a peak DR of 83.7 dB, corresponding to a 400-mVPP linear input range. The $\Delta \Sigma $ M’s 173.8-dB figure of merit (FoMDR) indicates its superior energy efficiency. The ASIC is assembled into a prototype of NeuroFlare measuring $2.8 \,\, {\times } \,\, 3.5 \,\, {\times } \,\, 0.7$ mm3. The recorded light-evoked local field potential (LFP) verified the functionality of NeuroFlare in vivo.
本文介绍了一种名为NeuroFlare的无线微型植入式光电神经接口设备的发明,该设备能够同时进行神经记录和光学刺激。NeuroFlare的特点是采用180nm CMOS工艺制造的低功耗、双峰专用集成电路(ASIC)。为了支持NeuroFlare的高功耗光学刺激,ASIC采用了一种新颖的线性充电开关电容刺激(LC-SCS)结构。LC-SCS仅在1.2 v的供电电压下工作,可以以3倍于供电电压的驱动电压和高达12 mA的大电流脉冲照亮LED,同时保持86.4的高充电效率%. In addition, LC -SCS requires only one off-chip capacitor, greatly facilitating device miniaturization. To accurately record neural signals in the presence of stimulation artifacts, the ASIC employs a delta-sigma modulator ( $\Delta \Sigma $ M)-based recording front end with a wide dynamic range (DR) to directly digitize the neural signals. The $\Delta \Sigma $ M features a 2nd-order loop architecture implemented using a linearized transconductance-capacitor (Gm-C) integrator followed by an active noise-shaping (NS) successive approximation register (SAR) quantizer. The $\Delta \Sigma $ M with a power consumption of $9.8~{\mu }$ W provides a peak DR of 83.7 dB, corresponding to a 400-mVPP linear input range. The $\Delta \Sigma $ M’s 173.8-dB figure of merit (FoMDR) indicates its superior energy efficiency. The ASIC is assembled into a prototype of NeuroFlare measuring $2.8 \,\, {\times } \,\, 3.5 \,\, {\times } \,\, 0.7$ mm3. The recorded light-evoked local field potential (LFP) verified the functionality of NeuroFlare in vivo.
期刊介绍:
The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuits modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.