A 25–31-GHz Compact True Power Detector With >33-dB Dynamic Range and Intrinsic Phase Offset Compensation in 40-nm Bulk CMOS

IF 5.6 1区 工程技术 Q1 ENGINEERING, ELECTRICAL & ELECTRONIC IEEE Journal of Solid-state Circuits Pub Date : 2025-01-30 DOI:10.1109/JSSC.2025.3531911
Haoqi Qin;Junjie Gu;Hao Xu;Zhiwei Xu;Pengcheng Jia;Na Yan
{"title":"A 25–31-GHz Compact True Power Detector With >33-dB Dynamic Range and Intrinsic Phase Offset Compensation in 40-nm Bulk CMOS","authors":"Haoqi Qin;Junjie Gu;Hao Xu;Zhiwei Xu;Pengcheng Jia;Na Yan","doi":"10.1109/JSSC.2025.3531911","DOIUrl":null,"url":null,"abstract":"This article presents a compact mixer-based true power detector integrated within a Ka-band power amplifier (PA). By performing capacitive voltage sensing and inductive current sensing at the primary coil, the compact power detector eliminates the need for additional area-consuming passive components while still allowing the PA to maintain a single-ended antenna output. The control of magnetic coupling with the secondary coil is achieved by exploiting magnetic flux cancellation rather than increasing the physical distance between coils. The active mixer multiplying the voltage and current uses current bleeding technique that simultaneously suppresses the flicker noise and enhances linearity, leading to a state-of-art dynamic range. Without phase shifters or resistor termination, the overall power detector achieves intrinsic phase compensation by matching the delays between the voltage and current sensing paths. Fabricated in a 40-nm CMOS process, the power detector occupies a core area of <inline-formula> <tex-math>$3520~\\mu $ </tex-math></inline-formula>m2 and covers a detectable power range from −18 to +15 dBm across 25–31 GHz with 12.1-mW power consumption.","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"60 5","pages":"1570-1583"},"PeriodicalIF":5.6000,"publicationDate":"2025-01-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Journal of Solid-state Circuits","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10858173/","RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q1","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
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Abstract

This article presents a compact mixer-based true power detector integrated within a Ka-band power amplifier (PA). By performing capacitive voltage sensing and inductive current sensing at the primary coil, the compact power detector eliminates the need for additional area-consuming passive components while still allowing the PA to maintain a single-ended antenna output. The control of magnetic coupling with the secondary coil is achieved by exploiting magnetic flux cancellation rather than increasing the physical distance between coils. The active mixer multiplying the voltage and current uses current bleeding technique that simultaneously suppresses the flicker noise and enhances linearity, leading to a state-of-art dynamic range. Without phase shifters or resistor termination, the overall power detector achieves intrinsic phase compensation by matching the delays between the voltage and current sensing paths. Fabricated in a 40-nm CMOS process, the power detector occupies a core area of $3520~\mu $ m2 and covers a detectable power range from −18 to +15 dBm across 25–31 GHz with 12.1-mW power consumption.
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具有> - 33db动态范围和固有相位偏移补偿的25 - 31 ghz紧凑型真功率检测器
本文介绍了一种集成在ka波段功率放大器(PA)内的基于混频器的紧凑型真功率检测器。通过在初级线圈上执行电容电压感测和电感电流感测,紧凑型功率检测器消除了对额外面积消耗无源元件的需求,同时仍然允许PA保持单端天线输出。通过利用磁通抵消而不是增加线圈之间的物理距离来实现与次级线圈的磁耦合控制。有源混频器采用电压和电流倍增技术,同时抑制闪烁噪声并增强线性度,从而实现最先进的动态范围。不需要移相器或电阻端接,整个功率检测器通过匹配电压和电流传感路径之间的延迟来实现本征相位补偿。功率探测器采用40纳米CMOS工艺制造,核心面积为3520~\mu $ m2,可探测功率范围为- 18至+15 dBm,覆盖25-31 GHz,功耗为12.1 mw。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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来源期刊
IEEE Journal of Solid-state Circuits
IEEE Journal of Solid-state Circuits 工程技术-工程:电子与电气
CiteScore
11.00
自引率
20.40%
发文量
351
审稿时长
3-6 weeks
期刊介绍: The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuits modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.
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