Efficient Number Theoretic Transform accelerator on the versal platform powered by the AI Engine

Abstract

Lattice-based cryptography, essential for fully homomorphic encryption, primarily relies on the computationally intensive Number Theoretic Transform (NTT). This paper proposes an NTT accelerator based on AMD/Xilinx Versal ACAP and AI Engine (AIE), featuring data engines on Programmable Logic (PL) and compute engines on the AIE. For inter-core parallelism on the AIE array, we propose an efficient method that applies the communication avoidance strategy to meet resource constraints; for intra-core data parallelism, we explore the modular multiplication algorithm suitable for AIE’s SIMD processors, proposing optimized software to support extensive NTT parameters while ensuring efficiency. Specialized data units are also proposed to compensate the slow DDR interface, enhancing data flow and overall performance. Our design outperforms CPU-based solutions by an average of 8.30$\times$ and Tesla V100 GPU-based solutions by 1.44$\times$ to 1.89$\times$. Compared to most FPGA-based solutions, our approach shows shorter latency, improving by an average of 2.62$\times$, while ensuring scalability and flexibility.