Accurate Modeling and Elimination of Vertical Crossings for Multisampled Single-Phase DC–AC Converters

Abstract

The multisample-multiupdate (MSMU) scheme is an effective approach to reduce delay in digitally controlled power converters. However, basic MSMU leads to current distortion from the vertical crossing (VC) of the modulation signal and carrier signal, which loses the closed-loop regulation. Therefore, it is significant to predict and eliminate the VC to avoid its negative influences. This article proposes an accurate model of VC in multisampled single-phase dc–ac converters. The total digital delay, the duty ratio, and the proportional gain in the system are the critical factors. Then, a modulation compensator is proposed to eliminate VC based on the prediction of the modulation signal. When the vertical crossing is detected by prediction, the modulation signal is compensated to imitate natural sampling. The proposed method features lower current distortion than existing methods, and it enhances the dissipative region of the system because it avoids using filters that will introduce equivalent delay. Finally, the theoretical analysis is validated by the simulation and the experimental results.