{"title":"A 94.7-dB Dynamic Range Fully Passive Switched-Capacitor Low-Pass Filter With Enhanced Selectivity","authors":"Farzan Rezaei;Loai G. Salem","doi":"10.1109/JSSC.2025.3539170","DOIUrl":null,"url":null,"abstract":"In this article, a passive gain-boosting technique is employed to improve the bandpass gain, input-referred noise, and area usage of a charge-rotation switched-capacitor (CRSC) filter. In addition, a passive feedback network is introduced, creating a sharp transition between the passband and stopband, thereby enhancing noise and linearity performance compared to prior work employing active feedback. Furthermore, the utilization of the pipeline technique raises the sampling frequency to match the clock frequency. The proposed filter is fabricated in 0.18-<inline-formula> <tex-math>$\\mu $ </tex-math></inline-formula>m CMOS technology. Operating from 1.8 V, the measured power dissipation of the filter is 1.52 mW. By applying a 250-MHz clock, the cutoff frequency of the filter can be tuned from 428 kHz to 6.75 MHz, while the dc gain is fixed at 1.33 dB under different bandwidth settings. For a 3-dB cutoff frequency of 2.35 MHz, the measured in-band IIP3 and IIP2 are 25 and 56 dBm, while the out-of-band IIP3 and IIP2 are 22.4 and 71.4 dBm, respectively. The input-referred integrated noise over 110 kHz–2.35 MHz is <inline-formula> <tex-math>$8.58{\\mu }$ </tex-math></inline-formula>Vrms. Compared to prior art, the proposed filter presents competitive noise performance, area usage, and dynamic range (DR).","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"60 8","pages":"2724-2735"},"PeriodicalIF":5.6000,"publicationDate":"2025-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Journal of Solid-state Circuits","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10884547/","RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q1","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
In this article, a passive gain-boosting technique is employed to improve the bandpass gain, input-referred noise, and area usage of a charge-rotation switched-capacitor (CRSC) filter. In addition, a passive feedback network is introduced, creating a sharp transition between the passband and stopband, thereby enhancing noise and linearity performance compared to prior work employing active feedback. Furthermore, the utilization of the pipeline technique raises the sampling frequency to match the clock frequency. The proposed filter is fabricated in 0.18-$\mu $ m CMOS technology. Operating from 1.8 V, the measured power dissipation of the filter is 1.52 mW. By applying a 250-MHz clock, the cutoff frequency of the filter can be tuned from 428 kHz to 6.75 MHz, while the dc gain is fixed at 1.33 dB under different bandwidth settings. For a 3-dB cutoff frequency of 2.35 MHz, the measured in-band IIP3 and IIP2 are 25 and 56 dBm, while the out-of-band IIP3 and IIP2 are 22.4 and 71.4 dBm, respectively. The input-referred integrated noise over 110 kHz–2.35 MHz is $8.58{\mu }$ Vrms. Compared to prior art, the proposed filter presents competitive noise performance, area usage, and dynamic range (DR).
期刊介绍:
The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuits modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.