A 94.7-dB Dynamic Range Fully Passive Switched-Capacitor Low-Pass Filter With Enhanced Selectivity

IF 5.6 1区 工程技术 Q1 ENGINEERING, ELECTRICAL & ELECTRONIC IEEE Journal of Solid-state Circuits Pub Date : 2025-02-13 DOI:10.1109/JSSC.2025.3539170
Farzan Rezaei;Loai G. Salem
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Abstract

In this article, a passive gain-boosting technique is employed to improve the bandpass gain, input-referred noise, and area usage of a charge-rotation switched-capacitor (CRSC) filter. In addition, a passive feedback network is introduced, creating a sharp transition between the passband and stopband, thereby enhancing noise and linearity performance compared to prior work employing active feedback. Furthermore, the utilization of the pipeline technique raises the sampling frequency to match the clock frequency. The proposed filter is fabricated in 0.18- $\mu $ m CMOS technology. Operating from 1.8 V, the measured power dissipation of the filter is 1.52 mW. By applying a 250-MHz clock, the cutoff frequency of the filter can be tuned from 428 kHz to 6.75 MHz, while the dc gain is fixed at 1.33 dB under different bandwidth settings. For a 3-dB cutoff frequency of 2.35 MHz, the measured in-band IIP3 and IIP2 are 25 and 56 dBm, while the out-of-band IIP3 and IIP2 are 22.4 and 71.4 dBm, respectively. The input-referred integrated noise over 110 kHz–2.35 MHz is $8.58{\mu }$ Vrms. Compared to prior art, the proposed filter presents competitive noise performance, area usage, and dynamic range (DR).
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具有增强选择性的94.7 db动态范围全无源开关电容低通滤波器
本文采用无源增益增强技术来提高电荷旋转开关电容(CRSC)滤波器的带通增益、输入参考噪声和面积利用率。此外,还引入了一个被动反馈网络,在通带和阻带之间产生一个急剧的过渡,从而与采用主动反馈的先前工作相比,增强了噪声和线性性能。此外,利用流水线技术提高了采样频率以匹配时钟频率。该滤波器采用0.18- $\mu $ m CMOS工艺制造。工作电压为1.8 V,滤波器的实测功耗为1.52 mW。通过施加250 MHz时钟,滤波器的截止频率可以从428 kHz调谐到6.75 MHz,而在不同带宽设置下,直流增益固定在1.33 dB。当3db截止频率为2.35 MHz时,测量到的带内IIP3和IIP2分别为25和56 dBm,而带外IIP3和IIP2分别为22.4和71.4 dBm。110 kHz-2.35 MHz以上的输入参考集成噪声为$8.58{\mu}$ Vrms。与现有技术相比,所提出的滤波器具有具有竞争力的噪声性能、面积利用率和动态范围(DR)。
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来源期刊
IEEE Journal of Solid-state Circuits
IEEE Journal of Solid-state Circuits 工程技术-工程:电子与电气
CiteScore
11.00
自引率
20.40%
发文量
351
审稿时长
3-6 weeks
期刊介绍: The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuits modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.
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