Huaiyu Liu;Yang Lin;Pujia Xing;Guoxing Wang;Yan Liu
{"title":"PWM-Based Impedance Boosting Technique With Autonomous Background Calibration for VCO-Based Neural Front Ends","authors":"Huaiyu Liu;Yang Lin;Pujia Xing;Guoxing Wang;Yan Liu","doi":"10.1109/JSSC.2025.3539843","DOIUrl":null,"url":null,"abstract":"Adaptive impedance boosting for bio-signal acquisition front end is essential for wearable and implantable devices, where the sensor exhibits a high source impedance with a large spread. A pulsewidth-modulation (PWM)-based capacitively coupled chopped voltage-controlled oscillator (VCO)-based continuous-time <inline-formula> <tex-math>$\\mathrm {\\Delta \\Sigma }$ </tex-math></inline-formula> modulator (CTDSM) for bio-potential monitoring is presented in this article. A PWM-based positive feedback loop is proposed to cancel the coupling and decoupling effect inside the chip, thus boosting the input impedance with simplified calibration digital to analog converter (DAC). A frequency-domain loop stability detection is proposed to continuously monitor the VCO outputs with a fully digital implementation. Therefore, a background auto-calibration scheme is developed to achieve sub-second convergence time. The proposed VCO-based neural front end was fabricated in a 180-nm CMOS process. With a chopping frequency of 640 kHz, the prototype achieves 1.84-<inline-formula> <tex-math>$\\mu $ </tex-math></inline-formula>Vrms input-referred noise (IRN) from 0.07-Hz to 1-kHz bandwidth. With a linear input range of 150 mVpp, it exhibits an signal to noise and distortion ratio (SNDR) of 72.4 dB and a dynamic range (DR) of 90.2 dB. With a chopping frequency of 10 kHz, it exhibits an IRN of <inline-formula> <tex-math>$3.09~{\\mu }$ </tex-math></inline-formula>Vrms, an SNDR of 81.0 dB, and a DR of 85.7 dB. In addition, an input impedance of 8.73 G<inline-formula> <tex-math>$\\Omega $ </tex-math></inline-formula> is achieved at 2 Hz.","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"60 8","pages":"2854-2865"},"PeriodicalIF":5.6000,"publicationDate":"2025-02-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Journal of Solid-state Circuits","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10890975/","RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q1","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
Adaptive impedance boosting for bio-signal acquisition front end is essential for wearable and implantable devices, where the sensor exhibits a high source impedance with a large spread. A pulsewidth-modulation (PWM)-based capacitively coupled chopped voltage-controlled oscillator (VCO)-based continuous-time $\mathrm {\Delta \Sigma }$ modulator (CTDSM) for bio-potential monitoring is presented in this article. A PWM-based positive feedback loop is proposed to cancel the coupling and decoupling effect inside the chip, thus boosting the input impedance with simplified calibration digital to analog converter (DAC). A frequency-domain loop stability detection is proposed to continuously monitor the VCO outputs with a fully digital implementation. Therefore, a background auto-calibration scheme is developed to achieve sub-second convergence time. The proposed VCO-based neural front end was fabricated in a 180-nm CMOS process. With a chopping frequency of 640 kHz, the prototype achieves 1.84-$\mu $ Vrms input-referred noise (IRN) from 0.07-Hz to 1-kHz bandwidth. With a linear input range of 150 mVpp, it exhibits an signal to noise and distortion ratio (SNDR) of 72.4 dB and a dynamic range (DR) of 90.2 dB. With a chopping frequency of 10 kHz, it exhibits an IRN of $3.09~{\mu }$ Vrms, an SNDR of 81.0 dB, and a DR of 85.7 dB. In addition, an input impedance of 8.73 G$\Omega $ is achieved at 2 Hz.
期刊介绍:
The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuits modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.