PWM-Based Impedance Boosting Technique With Autonomous Background Calibration for VCO-Based Neural Front Ends

IF 5.6 1区 工程技术 Q1 ENGINEERING, ELECTRICAL & ELECTRONIC IEEE Journal of Solid-state Circuits Pub Date : 2025-02-17 DOI:10.1109/JSSC.2025.3539843
Huaiyu Liu;Yang Lin;Pujia Xing;Guoxing Wang;Yan Liu
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Abstract

Adaptive impedance boosting for bio-signal acquisition front end is essential for wearable and implantable devices, where the sensor exhibits a high source impedance with a large spread. A pulsewidth-modulation (PWM)-based capacitively coupled chopped voltage-controlled oscillator (VCO)-based continuous-time $\mathrm {\Delta \Sigma }$ modulator (CTDSM) for bio-potential monitoring is presented in this article. A PWM-based positive feedback loop is proposed to cancel the coupling and decoupling effect inside the chip, thus boosting the input impedance with simplified calibration digital to analog converter (DAC). A frequency-domain loop stability detection is proposed to continuously monitor the VCO outputs with a fully digital implementation. Therefore, a background auto-calibration scheme is developed to achieve sub-second convergence time. The proposed VCO-based neural front end was fabricated in a 180-nm CMOS process. With a chopping frequency of 640 kHz, the prototype achieves 1.84- $\mu $ Vrms input-referred noise (IRN) from 0.07-Hz to 1-kHz bandwidth. With a linear input range of 150 mVpp, it exhibits an signal to noise and distortion ratio (SNDR) of 72.4 dB and a dynamic range (DR) of 90.2 dB. With a chopping frequency of 10 kHz, it exhibits an IRN of $3.09~{\mu }$ Vrms, an SNDR of 81.0 dB, and a DR of 85.7 dB. In addition, an input impedance of 8.73 G $\Omega $ is achieved at 2 Hz.
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基于pwm的vco神经前端自主背景标定阻抗增强技术
生物信号采集前端的自适应阻抗增强对于可穿戴和可植入设备至关重要,其中传感器具有高源阻抗和大传播。本文提出了一种基于脉冲宽度调制(PWM)的电容耦合斩波压控振荡器(VCO)的连续时间$\mathrm {\Delta \Sigma }$调制器(CTDSM),用于生物电位监测。提出了一种基于pwm的正反馈回路,消除芯片内部的耦合和去耦效应,从而通过简化的校准数模转换器(DAC)提高输入阻抗。提出了一种频域环稳定性检测方法,通过全数字化实现对压控振荡器输出的连续监测。为此,开发了一种后台自动校准方案,以实现亚秒级的收敛时间。采用180nm CMOS工艺制作了基于vco的神经网络前端。斩波频率为640 kHz,样机在0.07 hz至1 kHz带宽范围内实现了1.84- $\mu $ Vrms输入参考噪声(IRN)。线性输入范围为150 mVpp,信噪比和失真比(SNDR)为72.4 dB,动态范围(DR)为90.2 dB。斩波频率为10 kHz, IRN为$3.09~{\mu }$ Vrms, SNDR为81.0 dB, DR为85.7 dB。此外,在2hz时实现了8.73 G $\Omega $的输入阻抗。
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来源期刊
IEEE Journal of Solid-state Circuits
IEEE Journal of Solid-state Circuits 工程技术-工程:电子与电气
CiteScore
11.00
自引率
20.40%
发文量
351
审稿时长
3-6 weeks
期刊介绍: The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuits modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.
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