A 6.78-MHz Wireless Power and Data Transfer System Achieving Simultaneous 48.6% End-to-End Efficiency and 4.0-Mb/s Forward Data Delivery With Interference-Free Rectifier
{"title":"A 6.78-MHz Wireless Power and Data Transfer System Achieving Simultaneous 48.6% End-to-End Efficiency and 4.0-Mb/s Forward Data Delivery With Interference-Free Rectifier","authors":"Quanrong Zhuang;Junyi Sun;Bo Li;Xusheng Zhang;Zixu Wang;Yi Shi;Hao Qiu","doi":"10.1109/JSSC.2025.3541290","DOIUrl":null,"url":null,"abstract":"Targeting implantable medical devices (IMDs), we presented a simultaneous wireless power and data transfer (WPDT) system, using the fundamental and harmonic components of the bridge inverter on the transmitter (TX) side to, respectively, deliver power and forward data. On the receiver (RX) side, we discovered the data-flipping problem using the conventional full-bridge rectifier (FBR), which is ascribed to the interference from its distorted input voltage (<inline-formula> <tex-math>${V} {_{\\text {AC}}}$ </tex-math></inline-formula>). This problem is solved by the proposed interference-free rectifier (IFR) featuring its low-distortion staircase <inline-formula> <tex-math>${V} {_{\\text {ac}}}$ </tex-math></inline-formula>. To further alleviate the crosstalk between power and data transfer, a tapped coil three-capacitor (TL3C) topology on the TX side together with a resonant topology on the RX side was proposed. The IFR IC was fabricated by a 0.18-<inline-formula> <tex-math>$\\mu $ </tex-math></inline-formula>m CMOS process, with which a 6.78-MHz WPDT system was implemented. Experimental results showed that compared with the conventional FBR, the interference voltage ratio (IVR) in the proposed IFR was reduced from −17 to −45.2 dB. At a distance of 6 mm, our system supported simultaneous 54.4-mW load power (<inline-formula> <tex-math>${P} {_{\\text {Load}}}$ </tex-math></inline-formula>) and 4.0-Mb/s forward data rate (DR) with 48.6% end-to-end efficiency (<inline-formula> <tex-math>$\\eta _{\\text {E2E}}$ </tex-math></inline-formula>). Both figure of merits (FoMs) for power and data transfer are the highest compared with previous results.","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"60 9","pages":"3283-3293"},"PeriodicalIF":5.6000,"publicationDate":"2025-02-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Journal of Solid-state Circuits","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10897927/","RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q1","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
Targeting implantable medical devices (IMDs), we presented a simultaneous wireless power and data transfer (WPDT) system, using the fundamental and harmonic components of the bridge inverter on the transmitter (TX) side to, respectively, deliver power and forward data. On the receiver (RX) side, we discovered the data-flipping problem using the conventional full-bridge rectifier (FBR), which is ascribed to the interference from its distorted input voltage (${V} {_{\text {AC}}}$ ). This problem is solved by the proposed interference-free rectifier (IFR) featuring its low-distortion staircase ${V} {_{\text {ac}}}$ . To further alleviate the crosstalk between power and data transfer, a tapped coil three-capacitor (TL3C) topology on the TX side together with a resonant topology on the RX side was proposed. The IFR IC was fabricated by a 0.18-$\mu $ m CMOS process, with which a 6.78-MHz WPDT system was implemented. Experimental results showed that compared with the conventional FBR, the interference voltage ratio (IVR) in the proposed IFR was reduced from −17 to −45.2 dB. At a distance of 6 mm, our system supported simultaneous 54.4-mW load power (${P} {_{\text {Load}}}$ ) and 4.0-Mb/s forward data rate (DR) with 48.6% end-to-end efficiency ($\eta _{\text {E2E}}$ ). Both figure of merits (FoMs) for power and data transfer are the highest compared with previous results.
期刊介绍:
The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuits modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.