Investigation of parametric variation, gate engineering, RF parameters and interface traps in SOI L-body double gate tunnel field effect transistor

Abstract

This article presents an in-depth analysis of the silicon-on-insulator (SOI) L-body double gate tunnel field effect transistor with a focus on radio frequency (RF) performance and interface traps. Addressing the need for low-power applications, this article investigates the optimization of device parameters such as gate-source overlap, gate-drain underlap, source and drain thickness, and work-function engineering. Our results demonstrate that the L-body double gate configuration enhances tunneling efficiency and mitigates ambipolar behavior, contributing to improved subthreshold swings and a higher switching current ratio. Using Sentaurus TCAD simulations, RF parameters, intrinsic gate delay and cut-off frequency are investigated, highlighting the influence of interface traps on device behavior under varying trap distributions. This comprehensive study underscores the advantages of the proposed TFET structure for low power performance and high efficiency in RF applications.