A Dual-Inductor Quad-Path Hybrid Buck (2L4PHB) Converter With Reduced Inductor Current

IF 5.6 1区 工程技术 Q1 ENGINEERING, ELECTRICAL & ELECTRONIC IEEE Journal of Solid-state Circuits Pub Date : 2025-02-27 DOI:10.1109/JSSC.2025.3543582
Wen-Liang Zeng;Guigang Cai;Yan Lu;Sai-Weng Sin;Rui P. Martins;Chi-Seng Lam
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Abstract

In high-efficiency 12-to-1–1.8-V applications, the small duty ratio ( ${D}~{\approx }~0.1$ ) and high voltage stress on power switches of the conventional buck converter bring significant efficiency penalty. This article proposes a dual-inductor quad-path hybrid buck (2L4PHB) converter that addresses these issues, achieving both high power conversion efficiency and power density. Compared to the widely used double step-down (DSD) converter, the proposed 2L4PHB converter reduces the average inductor current by 30% and the inductor current ripple by 18% at a voltage conversion ratio (VCR) of 0.15. In addition to continuous conduction mode (CCM), this design incorporates a discontinuous conduction mode (DCM) calibration loop to improve efficiency at light loads. The proposed 2L4PHB converter, fabricated in a 180-nm BCD process, achieves a maximum current density of 0.18 A/mm2 and 256 A/cm3 and a peak efficiency of 93.7% and maintains efficiencies above 85% across load currents ranging from 0.6 to 4 A, all while using a compact inductor with dimensions of $2.5 {\times } 2.0 {\times } 1.0$ mm3 and a DCR of 48 m $\Omega $ .
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电感电流减小的双电感四路混合降压(2L4PHB)转换器
在高效的12- 1 - 1.8 v应用中,传统降压转换器的小占空比(${D}~{\approx }~0.1$)和功率开关上的高电压应力带来了显着的效率损失。本文提出了一种双电感四路混合降压(2L4PHB)转换器,解决了这些问题,实现了高功率转换效率和功率密度。与目前广泛使用的双降压(DSD)变换器相比,本文提出的2L4PHB变换器将电感平均电流降低30% and the inductor current ripple by 18% at a voltage conversion ratio (VCR) of 0.15. In addition to continuous conduction mode (CCM), this design incorporates a discontinuous conduction mode (DCM) calibration loop to improve efficiency at light loads. The proposed 2L4PHB converter, fabricated in a 180-nm BCD process, achieves a maximum current density of 0.18 A/mm2 and 256 A/cm3 and a peak efficiency of 93.7% and maintains efficiencies above 85% across load currents ranging from 0.6 to 4 A, all while using a compact inductor with dimensions of $2.5 {\times } 2.0 {\times } 1.0$ mm3 and a DCR of 48 m $\Omega $ .
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来源期刊
IEEE Journal of Solid-state Circuits
IEEE Journal of Solid-state Circuits 工程技术-工程:电子与电气
CiteScore
11.00
自引率
20.40%
发文量
351
审稿时长
3-6 weeks
期刊介绍: The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuits modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.
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