Review and Analysis of FPGA and ASIC Implementations of NIST Lightweight Cryptography Finalists

Abstract

The National Institute of Standards and Technology (NIST) initiated the lightweight cryptography (LWC) competition to facilitate Internet of Things (IoT) application security. This review explores hardware implementations of the NIST LWC finalists, studying their performance. A detailed comparison of FPGA and ASIC implementations is provided, summarizing both straightforward and optimized designs. It serves as a valuable resource for engineers and researchers, aiding in the selection of algorithms tailored to specific IoT application requirements. ASCON emerges as the most balanced performer, offering excellent throughput, area efficiency, and security. Meanwhile, TinyJAMBU and Grain128-AEAD excel in constrained environments and low-latency use cases.