Time-Frame Integrate-and-Fire Neuron Circuit for Low Energy Inference Hardware Spiking Neural Networks

Abstract

Hardware spiking neural networks (SNNs) are gaining increasing attention as promising next-generation computing approaches owing to their parallel computing and energy-efficient nature. Recent SNNs have achieved excellent performance by introducing artificial neural networks (ANN) to the SNN conversion training method. However, SNNs face significant challenges when implemented on hardware platforms. These challenges include achieving low energy consumption, difficulties in minimizing conversion error, and representing ANN functions other than the rectified linear unit activation function. This paper proposes mixed-signal complementary metal-oxide-semiconductor time-frame integrate-and-fire (TIF) neuron circuits and corresponding SNNs to achieve high accuracy with low energy consumption. TIF neurons integrate synaptic inputs during a time-frame and generate output spikes under synchronization signals based on the integrated input. When building SNNs with TIF neurons, bias and max-pooling can be effectively implemented, which is difficult to achieve using conventional SNNs with integrate-and-fire (IF) neuron circuits. In addition, TIF neurons support pipelining operations, further enhancing the inference throughput of the system. Simulation results with the CIFAR-10 dataset show that SNNs with TIF neurons achieve 0.48 %p higher classification accuracy while consuming 92 % lower neuron energy than conventional IF-based SNNs.