A TTD-Based Fast Precise Localization Enabled by Passive-Active Signal Combiner With Negative-Capacitance Stabilized RAMP

IF 5.6 1区 工程技术 Q1 ENGINEERING, ELECTRICAL & ELECTRONIC IEEE Journal of Solid-state Circuits Pub Date : 2025-03-18 DOI:10.1109/JSSC.2025.3546958
Qiuyan Xu;Aditya Wadaskar;Foad Beheshti;Chung-Ching Lin;Huan Hu;Danijela Cabric;Subhanshu Gupta
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Abstract

Fast and precise localization is one of critical requirements awaiting solutions in radar and communication systems. Spatio-spectral mapping has been proven as an effective methodology to estimate the angle-of-arrival (AoA) with low latency. In this work, we achieve a low AoA estimation error compared to prior integrated works by implementing a large delay-bandwidth (BW) product in the spatial signal processor (SSP) which correspondingly challenges the hardware design for multi-antenna analog/hybrid arrays. This work presents a two-channel 1.5-GHz BW true-time-delay (TTD)-based signal combiner with maximum 10 ns delay range demonstrating fast chirp-based source localization [also, beamtraining (BT)] for the first time. The measured AoA estimation error is significantly reduced from ±7.8° to ±1.1° with 15X increase in delay. This system-level solution is enabled by an integrated multistage switched-capacitor-array (MS-SCA) architecture including digitally controllable clock generator for large TTD, and a passive-active ring-amplifier (RAMP)-based signal combiner to overcome the BW trade-offs in conventional amplifier-based signal combiners. Further, a reduced gate-load bootstrapped switch and a negative-capacitance stabilized RAMP is proposed to support large BW operation. The proposed TTD-based MS-SCA achieves large delay-BW products of 15. The core design of this system consumes 37.3 mW/channel and 0.45 mm2 in 65 nm CMOS.
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基于负电容稳定RAMP的无源-有源信号组合器实现ttd的快速精确定位
快速和精确的定位是雷达和通信系统中等待解决方案的关键要求之一。空间光谱映射已被证明是一种有效的低延迟到达角估计方法。在这项工作中,我们通过在空间信号处理器(SSP)中实现大延迟带宽(BW)产品,与先前的集成工作相比,实现了低AoA估计误差,这相应地挑战了多天线模拟/混合阵列的硬件设计。这项工作首次提出了一种基于双通道1.5 ghz BW实时延迟(TTD)的信号合并器,其最大延迟范围为10 ns,展示了基于啁啾的快速源定位[也称为波束训练(BT)]。测量的AoA估计误差从±7.8°显著降低到±1.1°,延迟增加了15倍。该系统级解决方案由集成的多级开关电容阵列(MS-SCA)架构实现,包括用于大型TTD的数字可控时钟发生器,以及基于无源有源环形放大器(RAMP)的信号合并器,以克服传统基于放大器的信号合并器的BW权衡。此外,还提出了一种减小门负载自举开关和负电容稳定RAMP,以支持大BW运行。提出的基于ttd的MS-SCA实现了15的大延迟bw产品。该系统的核心设计功耗为37.3 mW/通道,在65 nm CMOS中消耗0.45 mm2。
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来源期刊
IEEE Journal of Solid-state Circuits
IEEE Journal of Solid-state Circuits 工程技术-工程:电子与电气
CiteScore
11.00
自引率
20.40%
发文量
351
审稿时长
3-6 weeks
期刊介绍: The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuits modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.
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