{"title":"A TTD-Based Fast Precise Localization Enabled by Passive-Active Signal Combiner With Negative-Capacitance Stabilized RAMP","authors":"Qiuyan Xu;Aditya Wadaskar;Foad Beheshti;Chung-Ching Lin;Huan Hu;Danijela Cabric;Subhanshu Gupta","doi":"10.1109/JSSC.2025.3546958","DOIUrl":null,"url":null,"abstract":"Fast and precise localization is one of critical requirements awaiting solutions in radar and communication systems. Spatio-spectral mapping has been proven as an effective methodology to estimate the angle-of-arrival (AoA) with low latency. In this work, we achieve a low AoA estimation error compared to prior integrated works by implementing a large delay-bandwidth (BW) product in the spatial signal processor (SSP) which correspondingly challenges the hardware design for multi-antenna analog/hybrid arrays. This work presents a two-channel 1.5-GHz BW true-time-delay (TTD)-based signal combiner with maximum 10 ns delay range demonstrating fast chirp-based source localization [also, beamtraining (BT)] for the first time. The measured AoA estimation error is significantly reduced from ±7.8° to ±1.1° with 15X increase in delay. This system-level solution is enabled by an integrated multistage switched-capacitor-array (MS-SCA) architecture including digitally controllable clock generator for large TTD, and a passive-active ring-amplifier (RAMP)-based signal combiner to overcome the BW trade-offs in conventional amplifier-based signal combiners. Further, a reduced gate-load bootstrapped switch and a negative-capacitance stabilized RAMP is proposed to support large BW operation. The proposed TTD-based MS-SCA achieves large delay-BW products of 15. The core design of this system consumes 37.3 mW/channel and 0.45 mm2 in 65 nm CMOS.","PeriodicalId":13129,"journal":{"name":"IEEE Journal of Solid-state Circuits","volume":"60 9","pages":"3202-3217"},"PeriodicalIF":5.6000,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Journal of Solid-state Circuits","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10931777/","RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q1","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
Fast and precise localization is one of critical requirements awaiting solutions in radar and communication systems. Spatio-spectral mapping has been proven as an effective methodology to estimate the angle-of-arrival (AoA) with low latency. In this work, we achieve a low AoA estimation error compared to prior integrated works by implementing a large delay-bandwidth (BW) product in the spatial signal processor (SSP) which correspondingly challenges the hardware design for multi-antenna analog/hybrid arrays. This work presents a two-channel 1.5-GHz BW true-time-delay (TTD)-based signal combiner with maximum 10 ns delay range demonstrating fast chirp-based source localization [also, beamtraining (BT)] for the first time. The measured AoA estimation error is significantly reduced from ±7.8° to ±1.1° with 15X increase in delay. This system-level solution is enabled by an integrated multistage switched-capacitor-array (MS-SCA) architecture including digitally controllable clock generator for large TTD, and a passive-active ring-amplifier (RAMP)-based signal combiner to overcome the BW trade-offs in conventional amplifier-based signal combiners. Further, a reduced gate-load bootstrapped switch and a negative-capacitance stabilized RAMP is proposed to support large BW operation. The proposed TTD-based MS-SCA achieves large delay-BW products of 15. The core design of this system consumes 37.3 mW/channel and 0.45 mm2 in 65 nm CMOS.
期刊介绍:
The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits. It also provides coverage of topics such as circuits modeling, technology, systems design, layout, and testing that relate directly to IC design. Integrated circuits and VLSI are of principal interest; material related to discrete circuit design is seldom published. Experimental verification is strongly encouraged.