Design Considerations of High- Frequency-Reference Fractional- N PLL: Architecture and Nonidealities

Abstract

This work presents two calibration-free 7-nm phase-locked loop (PLL) prototypes with high-frequency reference (high-ref): a 240-MHz-driven conventional xor-phase-detector-based PLL and a 2285-MHz-driven harmonic-mixing (HM) PLL, achieving FoMs of −258 and −261 dB, respectively. A frequency-domain analysis of the phase detector’s (PD’s) linearity and gain validates the xor PD as an optimal choice for high-ref PLL architectures. In addition, a first-order pulse-position modulation (PPM) noise model, which arises in high-ref PLLs, is incorporated into Perrott’s existing delta-sigma modulator (DSM) noise model, providing guidance on the choice of reference frequency in high-ref PLL architectures.