A Digital-Sampling PLL With a Second-Order Noise Shaping SAR ADC Phase Detector

Abstract

An integer-N digital-sampling phase-locked loop (PLL) based on a noise-shaping SAR (NS-SAR) analog-to-digital converter (ADC) breaks the quantization noise limitation of prior ADC-based phase detectors and enables the use of a lower resolution ADC quantizer and capacitive digital to analog converter (CDAC). Additionally, this improved ADC resolution reduces the phase-detector gain requirement and improves the lock performance. The 2nd-order noise-shaping of the NS-SAR ADC improves the time-to-voltage resolution of the phase detector by reducing in-band quantization noise and ADC input-referred noise (e.g., comparator noise). Measurements verify that noise shaping reduces the in-band noise by about 7 dB. The 28 nm CMOS prototype PLL operates at 4.3 GHz and consumes 13.7 mW. The measured rms integrated jitter from 1 kHz to 100 MHz is 133 fs.