Thor: A Non-Speculative Value Dependent Timing Side Channel Attack Exploiting Intel AMX

IF 1.4 3区 计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Computer Architecture Letters Pub Date : 2025-02-27 DOI:10.1109/LCA.2025.3544989
Farshad Dizani;Azam Ghanbari;Joshua Kalyanapu;Darsh Asher;Samira Mirbagher Ajorpaz
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Abstract

The rise of on-chip accelerators signifies a major shift in computing, driven by the growing demands of artificial intelligence (AI) and specialized applications. These accelerators have gained popularity due to their ability to substantially boost performance, cut energy usage, lower total cost of ownership (TCO), and promote sustainability. Intel's Advanced Matrix Extensions (AMX) is one such on-chip accelerator, specifically designed for handling tasks involving large matrix multiplications commonly used in machine learning (ML) models, image processing, and other computational-heavy operations. In this paper, we introduce a novel value-dependent timing side-channel vulnerability in Intel AMX. By exploiting this weakness, we demonstrate a software-based, value-dependent timing side-channel attack capable of inferring the sparsity of neural network weights without requiring any knowledge of the confidence score, privileged access or physical proximity. Our attack method can fully recover the sparsity of weights assigned to 64 input elements within 50 minutes, which is 631% faster than the maximum leakage rate achieved in the Hertzbleed attack.
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雷神:利用英特尔AMX的非投机值依赖定时侧信道攻击
在人工智能(AI)和专业应用日益增长的需求的推动下,片上加速器的兴起标志着计算领域的重大转变。这些加速器之所以受到欢迎,是因为它们能够大幅提高性能、减少能源使用、降低总拥有成本(TCO),并促进可持续性。英特尔的高级矩阵扩展(AMX)就是这样一种芯片上加速器,专门设计用于处理涉及大型矩阵乘法的任务,通常用于机器学习(ML)模型、图像处理和其他计算量大的操作。在本文中,我们介绍了一种新的英特尔AMX中与值相关的定时旁信道漏洞。通过利用这一弱点,我们展示了一种基于软件的、依赖于值的定时侧信道攻击,该攻击能够推断神经网络权重的稀疏性,而无需了解置信度评分、特权访问或物理接近度。我们的攻击方法可以在50分钟内完全恢复分配给64个输入元素的权值的稀疏性,比Hertzbleed攻击所达到的最大泄漏速率快631%。
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来源期刊
IEEE Computer Architecture Letters
IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-
CiteScore
4.60
自引率
4.30%
发文量
29
期刊介绍: IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.
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