Design of a Real Time FPGA-based Three Dimensional Positioning Algorithm.

Nathan G Johnson-Williams, Robert S Miyaoka, Xiaoli Li, Tom K Lewellen, Scott Hauck
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引用次数: 13

Abstract

We report on the implementation and hardware platform of a real time Statistics-Based Processing (SBP) method with depth of interaction processing for continuous miniature crystal element (cMiCE) detectors using a sensor on the entrance surface design. Our group previously reported on a Field Programmable Gate Array (FPGA) SBP implementation that provided a two dimensional (2D) solution of the detector's intrinsic spatial resolution. This new implementation extends that work to take advantage of three dimensional (3D) look up tables to provide a 3D positioning solution that improves intrinsic spatial resolution. Resolution is most improved along the edges of the crystal, an area where the 2D algorithm's performance suffers. The algorithm allows an intrinsic spatial resolution of ~0.90 mm FWHM in X and Y and a resolution of ~1.90 mm FWHM in Z (i.e., the depth of the crystal) based upon DETECT2000 simulation results that include the effects of Compton scatter in the crystal. A pipelined FPGA implementation is able to process events in excess of 220k events per second, which is greater than the maximum expected coincidence rate for an individual detector. In contrast to all detectors being processed at a centralized host, as in the current system, a separate FPGA is available at each detector, thus dividing the computational load. A prototype design has been implemented and tested using a reduced word size due to memory limitations of our commercial prototyping board.

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基于fpga的实时三维定位算法设计。
本文报道了一种基于统计的实时处理(SBP)方法的实现和硬件平台,该方法具有深度交互处理,用于连续微型晶体元件(cMiCE)探测器的入口表面设计。我们的团队之前报道了一种现场可编程门阵列(FPGA) SBP实现,该实现提供了探测器固有空间分辨率的二维(2D)解决方案。这个新的实现扩展了这项工作,利用三维(3D)查找表来提供3D定位解决方案,从而提高了固有的空间分辨率。分辨率在晶体边缘得到最大提高,这是二维算法性能受损的区域。基于DETECT2000模拟结果(包括晶体中的康普顿散射效应),该算法在X和Y上的固有空间分辨率为~0.90 mm FWHM,在Z(即晶体深度)上的分辨率为~1.90 mm FWHM。流水线FPGA实现能够以每秒超过220k个事件的速度处理事件,这比单个检测器的最大预期巧合率要高。与在一个集中的主机上处理所有探测器不同,在当前系统中,每个探测器都有一个单独的FPGA,从而划分了计算负载。由于我们的商业原型板的内存限制,原型设计已经实现并使用缩小的字长进行了测试。
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