Hardware Accelerated Reusable Merkle Tree Generation for Bitcoin Blockchain Headers

IF 1.4 3区 计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IEEE Computer Architecture Letters Pub Date : 2023-06-28 DOI:10.1109/LCA.2023.3289515
Kiseok Jeon;Junghee Lee;Bumsoo Kim;James J. Kim
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Abstract

As the value of Bitcoin increases, the difficulty level of mining keeps increasing. This is generally addressed with application-specific integrated circuits (ASIC), but block candidates are still created by the software. The overhead of block candidate generation is relatively growing because the hash computation is boosted by ASIC. Additionally, it is getting harder to find the target nonce; If it is not found for a block candidate, a new block candidate must be generated. A new candidate can be generated to reduce the overhead of block candidate generation by modifying the coinbase without selecting and verifying transactions again. To this end, we propose a hardware accelerator for generating Merkle trees efficiently. The hash computation for Merkle tree generation is conducted with ASIC to reduce the overhead of block candidate generation, and the tree with only the modified coinbase is rapidly regenerated by reusing the intermediate results of the previously generated tree. Our simulation results demonstrate that the execution time can be reduced by up to 98.92% and power consumption by up to 99.73% when the number of transactions in a tree is 2048.
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用于比特币区块链头的硬件加速可重用Merkle树生成
随着比特币价值的增加,挖矿的难度也在不断增加。这通常通过专用集成电路(ASIC)来解决,但块候选者仍然由软件创建。块候选生成的开销相对增长,因为ASIC提高了哈希计算。此外,查找目标nonce变得越来越困难;如果找不到块候选,则必须生成新的块候选。可以生成新的候选,以通过修改coinbase来减少块候选生成的开销,而无需再次选择和验证事务。为此,我们提出了一种有效生成Merkle树的硬件加速器。Merkle树生成的哈希计算是用ASIC进行的,以减少块候选生成的开销,并且通过重用先前生成的树的中间结果来快速再生仅具有修改的coinbase的树。我们的仿真结果表明,当树中的事务数为2048时,执行时间可以减少98.92%,功耗可以减少99.73%。
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来源期刊
IEEE Computer Architecture Letters
IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-
CiteScore
4.60
自引率
4.30%
发文量
29
期刊介绍: IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.
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