Multilayer Metallization Systems of Submicron Integrated Circuits

Abstract

The creation of a multilevel system of interconnections in submicron integrated circuits makes it possible to reduce the electrical resistance of conductive tracks, parasitic capacitance between conductors, and increase the speed of microelectronic devices. It is proposed to form a transverse profile of the current-carrying tracks of a multilayer metallization system in the form of an isosceles trapezoid with angles at the lower base equal to 75–85 degrees. Etching of an aluminum-based alloy film is carried out in a plasma gas mixture of BCl3, Cl2, and N2 at the pressure of 150–250 mTorr and power density of 1.6–2.2 W/cm2, with the following component content, vol.%: BCl3 – 50–65; Cl2 – 25–35; N2 – the rest.